Granted Patent B2

US 9,236,344 · App. 14/570,179 · Granted Jan 12, 2016

Abstract

Claims (26)

1. A semiconductor device, comprising:

a substrate having first and second circuits formed therein;

an interconnect stack formed on the substrate to define a planar interconnect stack surface having first and second exposed interconnects physically separated from one another by an interlayer dielectric layer in the multi-layer interconnect stack; and

a focused ion beam deposited fuse layer, which may be selectively programmed, formed overlying the interlayer dielectric layer and in physical or electrical contact with the first and second exposed interconnects.

2. The semiconductor device of claim 1 , where the focused ion beam deposited fuse layer comprises a layer of at least one of the group consisting of Ta, Ti, TaN, TiN, Al, Au, Co, Cr, Cu, Fe, Mo, Nb, Ni, Pd, Pt, and W formed to a predetermined thickness of less than approximately 500 Angstroms.

3. The semiconductor device of claim 1 , where the focused ion beam deposited fuse layer comprises a metal-based layer formed to a predetermined thickness of approximately 100-500 Angstroms.

4. The semiconductor device of claim 1 , where the focused ion beam deposited fuse layer comprises an unetched self-passivating conductive layer which is positioned to electrically connect the first and second exposed interconnects.

5. The semiconductor device of claim 1 , where the interconnect stack comprises a damascene interconnect stack comprising a top planar interlayer dielectric layer in which the first and second exposed interconnects are formed with copper in a last metal layer.

6. The semiconductor device of claim 1 , further comprising an insulating layer located over the focused ion beam deposited fuse layer and interconnect stack.

7. The semiconductor device of claim 1 , where the focused ion beam deposited fuse layer comprises an unetched conductive layer comprising Ta, Ti, TaN, TiN, Al, Au, Co, Cr, Cu, Fe, Mo, MoSi, Nb, Ni, Pd, Pt, or W.

8. The semiconductor device of claim 1 , where the focused ion beam deposited fuse layer comprises an unetched conductive layer having a thickness of less than approximately 500 Angstroms.

9. The semiconductor device of claim 1 , where the focused ion beam deposited fuse layer overlaps with the first and second exposed interconnects without forming an overhang portion that also extends past the first and second exposed interconnects.

10. A programmable ion beam deposited fuse layer formed with a localized deposition process on an interconnect stack without applying an etch process, where the programmable ion beam deposited fuse layer electrically and physically connects first and second exposed interconnects formed in the interconnect stack.

11. The programmable ion beam deposited fuse layer of claim 10 , where the programmable ion beam deposited fuse layer comprises an unetched layer of at least one of the group consisting of Ta, Ti, TaN, TiN, Al, Au, Co, Cr, Cu, Fe, Mo, MoSi, Nb, Ni, Pd, Pt, and W.

12. The programmable ion beam deposited fuse layer of claim 10 , where the programmable ion beam deposited fuse layer comprises an unetched conductive layer having a predetermined thickness of less than approximately 500 Angstroms.

13. The programmable ion beam deposited fuse layer of claim 10 , where the interconnect stack comprises a damascene interconnect stack comprising a planar interlayer dielectric layer in which the first and second exposed interconnects are formed with copper in a last metal layer.

14. The programmable ion beam deposited fuse layer of claim 13 , where the planar interlayer dielectric layer comprises TEOS silicon dioxide, fluorinated TEOS silicon dioxide, low dielectric constant CVD, PECVD, PVD, or ALD oxide.

15. The programmable ion beam deposited fuse layer of claim 13 , where the interconnect stack does not include a protective layer formed to protect the planar interlayer dielectric layer from etching.

16. The programmable ion beam deposited fuse layer of claim 10 , where the programmable ion beam deposited fuse layer overlaps with the first and second exposed interconnects without forming an overhang portion that also extends past the first and second exposed interconnects.

17. The programmable ion beam deposited fuse layer of claim 10 , further comprising a passivation layer located over the programmable ion beam deposited fuse layer.

18. The programmable ion beam deposited fuse layer of claim 17 , where the passivation layer comprises a high-k silicon dioxide, oxynitride, metal-oxide, or silicon nitride layer located over the programmable ion beam deposited fuse layer.

19. The programmable ion beam deposited fuse layer of claim 17 , where the programmable ion beam deposited fuse layer comprises a self-passivating layer which is oxidized to form the passivation layer.

20. An integrated circuit device, comprising:

a multi-layer dual damascene interconnect stack comprising a planar interconnect interlayer dielectric layer in which are formed first and second exposed interconnects comprising copper that are physically separated from one another;

a focused ion beam deposited fuse layer of Ta, Ti, TaN, TiN, Al, Au, Co, Cr, Cu, Fe, Mo, MoSi, Nb, Ni, Pd, Pt, and W that is formed to a predetermined thickness of less than approximately 500 Angstroms without applying an etch process to electrically connect the first and second exposed interconnects, where the focused ion beam deposited fuse layer may be selectively programmed to physically sever the electrical connection of the first and second exposed interconnects, where the focused ion beam deposited fuse layer overlaps with the first and second exposed interconnects without forming an overhang portion that also extends past the first and second exposed interconnects; and

one or more passivation layers located over the focused ion beam deposited fuse layer.

Assignments (10)