Common pin for multi-die semiconductor package
View Patent ↗A semiconductor package has multiple dies and an interior power bar that extends within an interior space formed within the die flag between the dies. The bond pads located on the interior side of each die are wire-bonded to the interior power bar. Some embodiments may have more than two dies and/or more than one interior power bar between each pair of adjacent dies.
1. A semiconductor package, comprising:
a partially segmented die flag comprising two die pads separated by an interior space;
first and second power bars located side-by-side located in the interior space between the two die pads;
a plurality of peripheral leads surrounding the die flag, wherein at least one of the peripheral leads is integral with the at least one power bar;
two dies respectively mounted to the two die pads of the die flag;
a first plurality of bond wires connecting bond pads on exterior sides of each die to the peripheral leads;
a second plurality of bond wires connecting bond pads on an interior side of each die to the at least one power bar, wherein a first subset of the second plurality of bond wires connect a first subset of the bond pads on the interior side of each die to the first power bar, and a second subset of the second plurality of bond wires connect a second subset of the bond pads on the interior side of each die to the second power bar.
2. The semiconductor package of claim 1 , wherein the first and second power bars provide two different external voltages to the two dies.
3. The semiconductor device of claim 1 , wherein the interior space is rectangular shaped.
4. The semiconductor device of claim 1 , wherein the interior space is closed at one end.