Memory device redundancy management system
View Patent ↗A system for managing redundancy in a memory device includes memory arrays and associated periphery logic circuits, and redundant memory arrays and associated redundant periphery logic circuits. The memory arrays and a first set of logic circuits associated with the periphery logic circuits corresponding to the memory arrays are connected to the power supply by way of memory I/O switches. The redundant memory arrays and associated redundant periphery logic circuits are connected to the power supply by way of redundant I/O switches. The memory and redundant I/O switches are switched on/off based on an acknowledgement signal generated during a built-in-self-test (BIST) operation of the memory device.
1. A system for managing redundancy in a memory device, wherein the memory device includes a first memory array and a first periphery logic circuit associated therewith, and at least one redundant memory array and a redundant periphery logic circuit associated therewith, wherein the first periphery logic circuit includes first and second logic circuits, and wherein the second logic circuit includes first and second sets of logic circuits, the system comprising:
a memory input/output (I/O) switch, connected to a power supply, the first memory array, and the first periphery logic circuit, wherein the memory I/O switch is configured to be switched on during a memory built-in-self-test (BIST) operation for detecting at least one defect in the first memory array and switched off for disabling a supply of power to the first memory array, the first logic circuit, and the first set of logic circuits, based on the detection of the at least one defect; and
a redundant I/O switch, connected to the power supply, the redundant memory array, and the redundant periphery logic circuit, wherein the redundant I/O switch is configured to be switched on when the redundant memory array and the redundant periphery logic circuit are substituted for the first memory array and the first periphery logic circuit, respectively, based on the detection of the at least one defect, and switched off when the redundant memory array and the redundant periphery logic circuit are not in use,
wherein the second set of logic circuits is connected to the power supply to receive a continuous supply of power therefrom to enable shifting of data stored in the first memory array to the redundant memory array, based on the detection of the at least one defect,
wherein the second logic circuit includes at least one of a read latch, an output driver, a write latch, and a redundancy decoder, and
wherein the read latch includes:
a first latch circuit connected to the power supply by way of the memory I/O switch and having a data input terminal connected to the first logic circuit, wherein the memory I/O switch disables a supply of power to the first latch circuit based on the detection of the at least one defect;
a first multiplexer having a first input terminal connected to an output terminal of the first latch circuit, a second input terminal connected to an output terminal of a second latch circuit corresponding to a second periphery logic circuit associated with a second memory array, and a select terminal for receiving a shift enable signal, wherein the first multiplexer selectively outputs at least one of the outputs of the first and second latch circuits at an output terminal thereof; and
a first buffer circuit having an input terminal connected to the output terminal of the first multiplexer and an output terminal that generates a read output of the first memory array, wherein the first multiplexer and the first buffer circuit are connected to the power supply for receiving the continuous supply of power.
2. The system of claim 1 , wherein the first logic circuit includes at least one of a column multiplexer, a sense amplifier, a sense amplifier driver, and a write driver.
3. The system of claim 1 , wherein the write latch includes:
a second multiplexer having a first input terminal connected to an output terminal of a second buffer circuit associated with the second periphery logic circuit, a second input terminal for receiving a data input signal, and a select terminal for receiving the shift enable signal, wherein the second multiplexer selectively provides at least one of an output of the second buffer circuit and the data input signal at an output terminal thereof;
a third latch circuit having a data input terminal connected to the output terminal of the second multiplexer;
a third buffer circuit having an input terminal connected to an output terminal of the third latch circuit and an output terminal connected to the first logic circuit, wherein the second multiplexer, the third latch circuit, and the third buffer circuit are connected to the power supply by way of the memory I/O switch, and wherein the memory I/O switch disables a supply of power to the second multiplexer, the third latch circuit, and the third buffer circuit based on the detection of the at least one defect; and
a fourth buffer circuit having an input terminal for receiving the data input signal and an output terminal connected to a third multiplexer associated with a third periphery logic circuit of a third memory array, wherein the fourth buffer circuit is connected to the power supply for receiving the continuous supply of power.
4. The system of claim 3 , wherein the switching of the memory and redundant I/O switches is controlled by an acknowledgement signal generated during the BIST operation.
5. The system of claim 4 , wherein the redundancy decoder decodes the acknowledgement signal to generate the shift enable signal.
6. The system of claim 4 , wherein the redundancy decoder is connected to the power supply for receiving the continuous supply of power.
7. The system of claim 3 , wherein the second set of logic circuits includes the first multiplexer, the first and fourth buffer circuits, and the redundancy decoder.
8. The system of claim 3 , wherein the first set of logic circuits includes the first latch circuit, the second multiplexer, the third latch circuit, and the third buffer circuit.
9. A memory device, comprising:
a first memory array for storing data;
a first periphery logic circuit associated with the first memory array, wherein the first periphery logic circuit includes first and second logic circuits, and wherein the second logic circuit includes first and second sets of logic circuits;
at least one redundant memory array;
a redundant periphery logic circuit associated with the at least one redundant memory array;
a memory I/O switch, connected to a power supply, the first memory array, and the first periphery logic circuit, wherein the memory I/O switch is switched on during a built-in-self-test (BIST) operation of the memory device for detecting at least one defect in the first memory array and switched off for disabling a supply of power to the first memory array, the first logic circuit, and the first set of logic circuits based on the detection of the at least one defect; and
a redundant I/O switch, connected to the power supply, the redundant memory array, and the redundant periphery logic circuit, wherein the redundant I/O switch is switched on when the redundant memory array and the redundant periphery logic circuit are substituted for the first memory array and the first periphery logic circuit, respectively, based on the detection of the at least one defect, and switched off when the redundant memory array and the redundant periphery logic circuit are not in use,
wherein the second set of logic circuits is connected to the power supply to receive a continuous supply of power therefrom to enable shifting of data stored in the first memory array to the redundant memory array, based on the detection of the at least one defect,
wherein the second logic circuit comprises at least one of a read latch, an output driver, a write latch, and a redundancy decoder, and
wherein the read latch includes:
a first latch circuit connected to the power supply by way of the memory I/O switch and having a data input terminal connected to the first logic circuit, wherein the memory I/O switch disables a supply of power to the first latch circuit based on the detection of the at least one defect;
a first multiplexer having a first input terminal connected to an output terminal of the first latch circuit, a second input terminal connected to an output terminal of a second latch circuit corresponding to a second periphery logic circuit associated with a second memory array, and a select terminal for receiving a shift enable signal, wherein the first multiplexer selectively outputs one of the outputs of the first and second latch circuits at an output terminal thereof; and
a first buffer circuit having an input terminal connected to the output terminal of the first multiplexer and an output terminal that generates a read output of the first memory array, wherein the first multiplexer and the first buffer circuit are connected to the power supply for receiving the continuous supply of power.
10. The memory device of claim 9 , wherein the first logic circuit includes at least one of a column multiplexers, a sense amplifier, a sense amplifier driver, and a write driver.
11. The memory device of claim 9 , wherein the write latch includes:
a second multiplexer having a first input terminal connected to an output terminal of a second buffer circuit associated with the second periphery logic circuit, a second input terminal for receiving a data input signal, and a select terminal for receiving the shift enable signal, wherein the second multiplexer selectively provides an output of the second buffer circuit and the data input signal at an output terminal thereof;
a third latch circuit having a data input terminal connected to the output terminal of the second multiplexer;
a third buffer circuit having an input terminal connected to an output terminal of the third latch circuit and an output terminal connected to the first logic circuit, wherein the second multiplexer, the third latch circuit, and the third buffer circuit are connected to the power supply by way of the memory I/O switch, wherein the memory I/O switch disables a supply of power to the second multiplexer, the third latch circuit, and the third buffer circuit based on the detection of the at least one defect; and
a fourth buffer circuit having an input terminal that receives the data input signal and an output terminal connected to a third multiplexer associated with a third periphery logic circuit of a third memory array, wherein the fourth buffer circuit is connected to the power supply for receiving the continuous supply of power.
12. The memory device of claim 11 , further comprising a BIST circuit that performs the BIST operation and generates an acknowledgement signal that controls the switching of the memory and redundant I/O switches, respectively.
13. The memory device of claim 11 , wherein the second set of logic circuits includes the first multiplexer, the first and fourth buffer circuits, and the redundancy decoder.
14. The memory device of claim 11 , wherein the first set of logic circuits includes the first latch circuit, the second multiplexer, the third latch circuit, and the third buffer circuit.
15. The memory device of claim 14 , wherein the redundancy decoder decodes the acknowledgement signal to generate the shift enable signal.
16. The memory device of claim 9 , wherein the memory device comprises at least one of a random-access memory (RAM), a flash memory, a dynamic random-access memory (DRAM), a static random-access memory (SRAM), a synchronous dynamic random-access memory (SDRAM), a single-data rate (SDR) SDRAM, and a double-data rate DDR SDRAM.