IP Library Granted Patent US 9,213,071
Granted Patent B2
US 9,213,071 · App. 13/663,998 · Granted Dec 15, 2015

Sensor single track trim using stationary hardware and fields

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Quick Facts
Patent No.
US 9,213,071
App. No.
13/663,998
Granted
Dec 15, 2015
Kind
B2
Abstract

A testing environment is provided in which both accelerometers and magnetometers can be tested in parallel, thereby decreasing the total cycle time for testing a semiconductor device package containing those devices. Embodiments of the present invention can also be configured to test singulated packages, thereby providing a tested and trimmed product that more accurately reflects the package delivered to the customer. In one embodiment, a series of device test locations within a testing region are configured to provide a known relationship with multiple fields of force. The device test locations are configured to provide sensitivity data from the packaged sensors in response to the directional forces. Embodiments provide a mechanism to transport the sensor packages from a device test location to a next device test location.

Claims (64)

1. A system comprising:

a test environment subject to a first vector associated with a first directional force and a second vector associated with a second directional force;

a device under test comprising a first set of directionally sensitive sensors sensitive to the first directional force and a second set of directionally sensitive sensors sensitive to the second directional force;

a first test location within the test environment, wherein

the first test location is positioned in a first known orientation to both the first and second vectors, and

the first test location is configured to receive the device under test and position the device under test in a fixed relationship to the first known orientation; and

a processor, communicatively coupled to the first test location, and configured to

receive signals from the device under test at the first test location, wherein the signals are responsive to the first set of directionally sensitive sensors response to the first directional force at the first known orientation and are responsive to the second set of directionally sensitive sensors response to the second directional force at the first known orientation, and

transmit one or more trim signals to the device under test.

2. The system of claim 1 wherein the one or more trim signals are responsive to the received signals from the device under test at the first test location.

3. The system of claim 1 wherein the first vector describing a direction of the first directional force and the second vector describing a direction of the second directional force are in alignment.

4. The system of claim 1 wherein the first test location is constructed of materials that maintain uniformity of the first and second directional forces.

5. The system of claim 1 , wherein

the first set of directionally sensitive sensors comprises a first set of three orthogonally oriented sensors, wherein the three orthogonally sensitive sensors are configured to respond to a magnetic field; and

the second set of directionally sensitive sensors comprises a second set of three orthogonally oriented sensors, wherein the second set of three orthogonally oriented sensors are configured to respond to an acceleration.

6. The system of claim 1 further comprising:

magnetic field generator configured to generate the first directional force, wherein the first directional force is uniform throughout the test environment.

7. The system of claim 6 wherein the magnetic field generator comprises a first Helmholtz coil and a second Helmholtz coil.

8. The system of claim 6 wherein the second directional force is gravity.

9. The system of claim 1 further comprising:

a second test location within the test environment, wherein

the second test location is positioned in a second known orientation to both the first and second vectors, wherein the second known orientation is different from the first known orientation, and

the second test location is configured to receive the device under test and position the device under test in a fixed relationship to the second known orientation; and

the processor is communicatively coupled to the second test location, and configured to

receive second signals from the device under test at the second test location, wherein the second signals are responsive to the first set of directionally sensitive sensors response to the first directional force at the second known orientation and are responsive to the second set of directionally sensitive sensors response to the second directional force at the second known orientation, and

transmit one or more second trim signals to the device under test, wherein the one or more second trim signals are responsive to the received signals from the device under test at the first test location and the second test location.

10. The system of claim 9 further comprising:

a feed mechanism configured to transport the device under test from the first test location to the second test location.

11. The system of claim 10 wherein the feed mechanism comprises a track along which the device under test can move from the first test location to the second test location.

12. The system of claim 10 wherein the feed mechanism comprises a mechanical mechanism configured to move the device under test from the first test location to the second test location.

13. A method for testing a semiconductor device package comprising first and second sets of directionally sensitive sensors, the first set sensitive to a first directional force and the second set sensitive to a second directional force, the method comprising:

orienting the semiconductor device package in a first known orientation to each of the first and second directional forces;

testing the first set of directionally sensitive sensors;

testing the second set of directionally sensitive sensors;

subsequent to said testing the first and second sets of directionally sensitive sensors, re-orienting the semiconductor device package to a second known orientation to each of the first and second directional forces.

14. The method of claim 13 wherein said orienting the semiconductor device package in a first known orientation to each of the first and second directional forces comprises:

providing a first test socket, wherein

the first test socket is configured to receive the semiconductor device package, and

the first test socket is oriented in the first known orientation to the first and second directional forces; and

inserting the semiconductor device package in the first test socket.

15. The method of claim 13 further comprising:

performing testing of the first and second sets of directionally sensitive sensors at the second known orientation to the first and second directional forces;

performing testing of the first and second sets of directionally sensitive sensors at one or more additional known orientations to each of the first and second directional forces;

collecting data corresponding to signals produced by the first and second sets of directionally sensitive sensors at each of the known orientations;

calculating trim information for the first and second sets of directionally sensitive sensors in response to the collected data; and

storing the trim information in a memory associated with the semiconductor device package.

16. The method of claim 13 wherein said testing the first set of directionally sensitive sensors comprises:

stimulating the first set of directionally sensitive sensors with the first directional force;

receiving a signal from the first set of directionally sensitive sensors, the signal responsive to said stimulating.

17. The method of claim 16 , wherein

the first set of directionally sensitive sensors are an orthogonally-oriented set of magnetometers, and

the first directional force is a magnetic field.

18. The method of claim 17 further comprising:

forming the magnetic field using a pair of Helmholtz coils, wherein

said forming the magnetic field is initiated before said orienting the semiconductor device package, and

the magnetic field is maintained throughout said testing and subsequent to said re-orienting.

19. The method of claim 16 wherein said testing the second set of directionally sensitive sensors comprises:

stimulating the second set of directionally sensitive sensors with the second directional force;

receiving a signal from the second set of directionally sensitive sensors, the signal responsive to said stimulating the second set of directionally sensitive sensors,

wherein

said stimulating the second set of directionally sensitive sensors is performed at about the same time as said stimulating the first set of directionally sensitive sensors.

20. The method of claim 19 , wherein

the second set of directionally sensitive sensors are an orthogonally oriented set of accelerometers, and

the second directional force field is gravity.

Assignments (21)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
MERGER Recorded Jan 3, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041144/0363 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
PATENT RELEASE Recorded Jan 14, 2016
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037494/0312 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0671 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0685 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Apr 22, 2013
From: FREESCALE SEMICONDUCTOR, INC.
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To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 30, 2012
From: SCHULTZ, PETER S.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 029217/0278 →