Wettable lead ends on a flat-pack no-lead microelectronic package
Methods of manufacturing a flat-pack no-lead microelectronic package ( 2100 ) coat exposed base metal at a cut end of a lead frame of the package with solder ( 1001 ). One method coats the exposed base metal with solder when the package is in a strip ( 200, 300 ). Another method coats the exposed base metal with solder after the package is singulated. As a result, all portions of leads of the package that may receive solder during mounting of the package to a printed circuit board are solder wettable. A solder wettable lead end ( 504 ) on the package facilitates formation of a solder fillet during mounting of the package.
1. A method of manufacturing a microelectronic package, comprising:
providing a lead frame strip that includes a plurality of lead frames, the lead frame strip having saw lanes between the lead frames;
encapsulating the lead frame strip;
after encapsulating, removing metal of the lead frame strip along the saw lanes;
after removing metal, applying solder to the lead frame strip;
reflowing the solder; and
singulating the lead frame strip into individual microelectronic packages after the reflowing.
2. The method of manufacturing a microelectronic package of claim 1 , wherein the step of removing includes removing by one of sawing and etching.
3. The method of manufacturing a microelectronic package of claim 1 , wherein the step of removing the metal from the lead frame strip along the saw lanes removes all metal from the lead frame strip along the saw lanes and maintains at least some mold compound along the saw lanes.
4. The method of manufacturing a microelectronic package of claim 1 , wherein the step of applying solder to the lead frame strip includes applying one of solder cream and solder paste (hereinafter “paste”) using a stencil having a pattern of openings whose locations correspond to location of leads of the lead frame strip.
5. The method of manufacturing a microelectronic package of claim 4 , wherein the step of applying solder to the lead frame strip includes applying paste to all portions of the lead frame that is not covered by mold compound.
6. The method of manufacturing a microelectronic package of claim 4 , wherein the step of applying solder to the lead frame strip includes applying paste to only along the saw lanes.
7. The method of manufacturing a microelectronic package of claim 1 , wherein base metal of the lead frame strip is not plated, and wherein the step of applying solder includes applying solder to a bottom of the lead frame.
8. The method of manufacturing a microelectronic package of claim 1 , wherein the step of reflowing the solder includes reflowing the solder until surfaces of bare base metal are covered with a coating of solder.
9. The method of manufacturing a microelectronic package of claim 1 , wherein the package is one of a quad flat-pack no-lead (QFN) package and a dual flat-pack no-lead (DFN) package.
10. A method of manufacturing a microelectronic package, comprising:
providing a lead frame strip that includes a plurality of lead frames, the lead frame strip having saw lanes between the lead frames;
encapsulating the lead frame strip;
after encapsulating the lead frame strip, applying solder to the lead frame strip;
reflowing the solder;
removing metal of the lead frame strip and the solder along the saw lanes, thereby creating a surface of bare base metal;
reflowing the solder; and
singulating the lead frame strip into individual microelectronic packages.
11. The method of manufacturing a microelectronic package of claim 10 , wherein step of applying solder to the lead frame strip includes applying one of solder cream and solder paste to only along the saw lanes.
12. The method of manufacturing a microelectronic package of claim 10 , including, subsequent to the step of removing metal and prior to the second step of reflowing, a step of adding flux to the bare base metal.
13. The method of manufacturing a microelectronic package of claim 12 , wherein the second step of reflowing the solder includes reflowing the solder until surfaces of bare base metal are covered with a coating of solder.
14. The method of manufacturing a microelectronic package of claim 10 , wherein the step of applying solder includes one of: screen printing, solder performs, solder balls, using solder jetting, and using nanoparticle printing/spraying.
15. The method of manufacturing a microelectronic package of claim 10 , wherein base metal of the lead frame strip is not plated, and wherein the step of applying solder includes applying one of solder cream and solder paste to an entire bottom of the lead frame.
16. The method of manufacturing a microelectronic package of claim 10 , wherein the package is one of a quad flat-pack no-lead (QFN) package and a dual flat-pack no-lead (DFN) package.
17. A method of manufacturing a microelectronic package, comprising:
a) providing a package that has at least one lead having a portion at a bottom of the package and a portion at a side of the package, wherein the at least one lead has a surface located in a plane approximately orthogonal to a plane of the bottom of the package;
b) applying solder to a solder carrier;
c) placing the package on the solder that is on the solder carrier, wherein cut lead ends of the package are aligned with the solder;
d) placing a combination of the package, the solder and the solder carrier on a reflow carrier; and
e) reflowing the solder until the surface of the at least one lead located in the plane approximately orthogonal to the plane of the bottom of the package becomes solder wettable.
18. The method of manufacturing a microelectronic package of claim 17 , including subsequent to step c) and prior to step d), a step of inverting the combination of the package, the solder and the solder carrier.
19. The method of manufacturing a microelectronic package of claim 17 , wherein the package is one of a quad flat-pack no-lead (QFN) package and a dual flat-pack no-lead (DFN) package.
20. The method of manufacturing a microelectronic package of claim 17 wherein the step of applying solder to the solder carrier includes applying solder to only certain portions of the solder carrier wherein the certain portions correspond to an area of the at least one lead and to an area adjacent to the at least one lead and slightly beyond a perimeter of the package.