IP Library Granted Patent US 8,890,612
Granted Patent B2
US 8,890,612 · App. 13/656,253 · Granted Nov 18, 2014

Dynamically biased output structure

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Quick Facts
Patent No.
US 8,890,612
App. No.
13/656,253
Granted
Nov 18, 2014
Kind
B2
Abstract

A transconductance amplification stage ( 301 ) includes a differential pair ( 306 ) wherein a bias current flows through each transistor ( 302, 304 ) of the pair when input voltages are equal. Tail current boosting circuitry ( 320 ), which includes a tail transistor, provides a translinear expansion of tail current of the differential pair. A feedback loop ( 307 ) dynamically biases the differential pair to maintain current through one transistor ( 302 ) of the pair at the bias current value in spite of a difference between input voltages. Another transistor ( 304 ) of the pair provides an output current responsive to a difference between input voltages. The output current is not affected by a region of operation of the tail transistor. An output structure ( 300, 500 ) includes the transconductance amplification stage and a circuit ( 303 ) for mirroring the output current. An amplifier ( 800 ) includes the output structure as a buffer between other structures ( 801 ) and an output terminal.

Claims (48)

1. An integrated circuit including a transconductance amplification stage, the transconductance amplification stage comprising:

a differential pair of transistors, wherein a first input terminal of the amplification stage includes a control electrode of a first transistor of the differential pair, wherein a second input terminal of the amplification stage includes a control electrode of a second transistor of the differential pair, and wherein a current equal to a bias current flows through a conducting electrode of the first transistor and through a conducting electrode of the second transistor when a first input voltage at the first input terminal is equal to a second input voltage at the second input terminal;

first circuitry, coupled to the conducting electrode of the first transistor and to a node, for providing a first current;

second circuitry, coupled to the node, for sinking a second current from the node, wherein the second current is equal to the first current minus the bias current;

tail current boosting circuitry, coupled to the node, for providing a translinear expansion of tail current of the differential pair, the tail current responsive to a voltage at the node;

a feedback loop that dynamically biases the differential pair by controlling the voltage at the node by negative feedback during operation,

wherein the current through the conducting electrode of the second transistor is maintained at a constant value during operation, and

wherein a conducting electrode of the first transistor provides an output current responsive to a difference between the first input voltage and the second input voltage; and

an output terminal for outputting the output current.

2. The integrated circuit of claim 1 , wherein the current through the conducting electrode of the second transistor remains, during operation, at the value of the bias current regardless of the difference between the first input voltage and the second input voltage.

3. The integrated circuit of claim 2 , wherein the feedback loop maintains the current through the conducting electrode of the second transistor constant by adjusting the voltage at the node.

4. The integrated circuit of claim 3 , wherein the tail current boosting circuitry provides an amount of tail current equal to two times the bias current when the first input voltage at the first input terminal is equal to the second input voltage at the second input terminal, and provides a tail current greater than two times the bias current when the first input voltage at the first input terminal is greater than the second input voltage at the second input terminal.

5. The integrated circuit of claim 3 , wherein the tail current boosting circuitry provides an amount of tail current that is representative of a difference between first input voltage at the first input terminal and the second input voltage at the second input terminal.

6. The integrated circuit of claim 1 , wherein the tail current boosting circuitry is coupled to a second conducting electrode of the first transistor and to a second conducting electrode of the second transistor.

7. The integrated circuit of claim 6 , wherein the tail current boosting circuitry includes a tail transistor having a conducting electrode coupled to the second conducting electrode of the first transistor and to the second conducting electrode of the second transistor, having a second conducting electrode coupled to a power supply terminal, and having a control electrode coupled to the node.

8. The integrated circuit of claim 7 , wherein the current through the conducting electrode of the first transistor is not affected by a region of operation of the tail transistor of the tail current boosting circuitry.

9. The integrated circuit of claim 7 , wherein the feedback loop compensates for a region of operation of the tail transistor of the tail current boosting circuitry.

10. The integrated circuit of claim 1 , wherein the first current is a fixed current having a magnitude equal to two times the bias current, and wherein the second current is a fixed current having a magnitude equal to the bias current.

11. The integrated circuit of claim 1 , wherein the second current is a fixed current that has, at all times when operating, a magnitude equal to a magnitude of current of the conducting electrode of the second transistor that occurs when the first input voltage at the first input terminal is equal to the second input voltage at the second input terminal.

12. An integrated circuit including a dynamically biased output structure of an amplifier, the dynamically biased output structure having a non-inverting input terminal for receiving a first input voltage, an inverting input terminal for receiving a second input voltage, and an output terminal for outputting an output voltage, comprising:

a transconductance amplification stage, including:

a differential pair of transistors, wherein a first input terminal of the amplification stage includes a control electrode of a first transistor of the differential pair, wherein a second input terminal of the amplification stage includes a control electrode of a second transistor of the differential pair, and wherein a current equal to a bias current flows through a conducting electrode of the first transistor and through a conducting electrode of the second transistor when a first input voltage at the first input terminal is equal to a second input voltage at the second input terminal,

first circuitry, coupled to the conducting electrode of the first transistor and to a node, for providing a first current,

second circuitry, coupled to the node, for sinking a second current from the node, wherein the second current is equal to the first current minus the bias current during operation,

tail current boosting circuitry, coupled to the node, for providing a translinear expansion of tail current of the differential pair, the tail current responsive to a voltage at the node, and

a feedback loop that dynamically biases the differential pair by controlling the voltage at the node by negative feedback,

wherein the current through the conducting electrode of the second transistor is maintained at a constant value, and wherein a conducting electrode of the first transistor provides a current responsive to a difference between the first input voltage and the second input voltage; and

a current mirror, coupled to the transconductance amplification stage, for providing an output current at the output terminal of the output structure, wherein the output current is equal in magnitude to the current of the first conducting electrode of the second transistor.

13. The integrated circuit of claim 12 , wherein the tail current boosting circuitry includes a tail transistor, wherein the feedback loop compensates for a region of operation of the tail transistor by controlling a voltage at a control electrode of the tail transistor, and wherein the current through the conducting electrode of the first transistor is not affected by a region of operation of the tail transistor.

14. The integrated circuit of claim 12 , wherein the output voltage at the output terminal of the output structure is representative of a difference between the first input voltage and the second input voltage.

15. The integrated circuit of claim 12 , including

an outer feedback loop that couples the output terminal of the output structure to the inverting input terminal of the amplification stage,

wherein the output voltage at the output terminal of the output structure is equal to the first input voltage at the non-inverting input terminal.

16. The integrated circuit of claim 15 , wherein the output terminal of the output structure is coupled to a load impedance, and the tail current dynamically changes in response to changes in the output voltage.

17. The integrated circuit of claim 15 , wherein the output terminal of the output structure is coupled to a load impedance, and the output current dynamically changes in response to changes in the output voltage.

18. The integrated circuit of claim 15 , wherein the output terminal of the output structure is coupled to a load impedance, and wherein the output voltage remains representative of the first input voltage during large-signal, rail-to-rail input transitions of the first input voltage.

19. An amplifier having at least an output terminal, comprising:

output circuitry having at least one input terminal for receiving an input voltage, and an output terminal coupled to the output terminal of the amplifier for outputting an output voltage, the output circuitry comprising:

a transconductance amplification stage, including:

a differential pair of transistors, wherein a first input terminal of the amplification stage includes a control electrode of a first transistor of the differential pair, wherein a second input terminal of the amplification stage includes a control electrode of a second transistor of the differential pair,

first circuitry, coupled to a conducting electrode of the first transistor and to a node, for providing a first current,

second circuitry, coupled to the node, for sinking a second current from the node, wherein the second current is equal to the first current minus a bias current of the differential pair during operation,

tail current boosting circuitry, coupled to the node, for providing a translinear expansion of a tail current of the differential pair, the tail current responsive to a voltage at the node; and

a feedback loop that dynamically biases the differential pair by controlling the voltage at the node by negative feedback,

wherein a current through a conducting electrode of the second transistor is maintained at a constant value, and wherein a conducting electrode of the first transistor provides a current responsive to a difference between a voltage at the first input terminal and a voltage at the second input terminal; and

a current mirror, coupled to the transconductance amplification stage, for providing an output current at the output terminal of the output circuitry, wherein the output current has a magnitude that is equal to or greater than a magnitude of the current through the first conducting electrode of the second transistor; and

other circuitry for providing the input voltage to the input terminal of the output circuitry, wherein the output circuitry acts as a buffer between the other circuitry and the output terminal of the amplifier.

20. The amplifier of claim 19 , wherein the other circuitry include a temperature sensor, and wherein the input voltage is an analog signal indicative of temperature of the amplifier.

Assignments (30)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
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From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
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CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
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From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
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MERGER Recorded Jan 3, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
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