IP Library Granted Patent US 8,680,621
Granted Patent B2
US 8,680,621 · App. 13/695,670 · Granted Mar 25, 2014

Integrated circuit, electronic device and ESD protection therefor

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Quick Facts
Patent No.
US 8,680,621
App. No.
13/695,670
Granted
Mar 25, 2014
Kind
B2
Abstract

An integrated circuit comprising electro-static discharge (ESD) protection circuitry arranged to provide ESD protection to an external terminal of the integrated circuit. The ESD protection circuitry comprises: a thyristor circuit comprising a first bipolar switching device operably coupled to the external terminal and a second bipolar switching device operably coupled to another external terminal, a collector of the first bipolar switching device being coupled to a base of the second bipolar switching device and a base of the first bipolar switching device being coupled to a collector of the second bipolar switching device. A third bipolar switching device is also provided and operably coupled to the thyristor circuit and has a threshold voltage for triggering the thyristor circuit, the threshold voltage being independently configurable of the thyristor circuit. The first and second switching devices are arranged so as to provide, when in use, a bidirectional snapback characteristic and a snapback voltage associated therewith.

Claims (29)

1. An integrated circuit comprising electro-static discharge, ESD, protection circuitry arranged to provide ESD protection to an external terminal of the integrated circuit, the ESD protection circuitry comprising:

a thyristor circuit comprising a first bipolar switching device operably coupled to the external terminal and a second bipolar switching device operably coupled to another external terminal, a collector of the first bipolar switching device being coupled to a base of the second bipolar switching device and a base of the first bipolar switching device being coupled to a collector of the second bipolar switching device; and

a third bipolar switching device having a base terminal operably coupled to the thyristor circuit and having a threshold voltage for triggering the thyristor circuit to provide a current path from the external terminal to the another external terminal, the threshold voltage being independently configurable of the thyristor circuit; wherein

the first and second switching devices, when in use, exhibiting a bidirectional snapback characteristic and a snapback voltage associated therewith.

2. A circuit as claimed in claim 1 , wherein the thyristor circuit is a Silicon-Controlled Rectifier.

3. A circuit as claimed in claim 1 , wherein the first bipolar switching device is a PNP bipolar transistor.

4. A circuit as claimed in claim 1 , wherein the second bipolar switching device is a first NPN bipolar transistor.

5. A circuit as claimed in claim 1 , wherein the third bipolar switching device is a second NPN bipolar transistor.

6. A circuit as claimed in claim 1 , wherein a base of the third switching device is also coupled to the collector of the first switching device.

7. A circuit as claimed in claim 1 , wherein an emitter of the second bipolar switching device is coupled to an emitter of the third bipolar switching device.

8. A circuit as claimed in claim 1 , wherein an emitter terminal of the first switching device is coupled to the external terminal via an external resistance.

9. A circuit as claimed in claim 1 , wherein the first bipolar switching device provides, when in use, a first current path from the collector to the emitter of the first bipolar switching device when a voltage across the external terminal and the another external terminal exceeds a trigger voltage, and the second bipolar switching device provides a second substantially lateral current path and a third substantially vertical current path.

10. A circuit as claimed in claim 9 , wherein the first bipolar switching device is arranged to provide, when a current associated with an electrostatic discharge event exceeds a predetermined trigger current value, a fourth substantially vertical current path that crosses the first current path, thereby providing thyristor functionality in response thereto.

11. A circuit as claimed in claim 1 , further comprising a semiconductor substrate and a layer of n-type material disposed adjacent the semiconductor substrate.

12. A circuit as claimed in claim 11 , further comprising:

a first p-region disposed in the n-type material and a second p-region disposed in the n-type material, the first and second p-regions being laterally spaced with respect to each other;

a first p+ region disposed between a first n+ region and a second n+ region in the first p-region, the first n+ region, the second n+ region and the first p+ region being laterally spaced with respect to each other; and

a third n+ region and a second p+ region disposed in the second p-region and laterally spaced with respect to each other.

13. A circuit as claimed in claim 12 , wherein the external terminal is operably coupled to the third n+ region and the second p+ region, the external terminal constituting a second common contact.

14. A circuit as claimed in claim 12 , wherein the another external terminal is operably coupled to the first n+ region, the first p+ region and the second n+ region, the another external terminal constituting a first common contact.

15. A circuit as claimed in claim 12 , wherein a lateral distance between the first p-region and the second p-region defines a snapback voltage of the thyristor circuit.

16. A circuit as claimed in claim 12 , further comprising:

a lateral isolation layer disposed opposite the first p-region, a lateral distance between the first p-region and the lateral isolation layer defining the trigger voltage for the thyristor circuit.

17. A circuit as claimed in claim 11 , wherein the layer of n-type material is operably coupled to a biasing element.

18. An electronic device comprising the integrated circuit of claim 1 .

19. A method of providing electro-static discharge, ESD, protection to an external terminal of an integrated circuit, the method comprising:

providing a thyristor circuit coupled across the external terminal and another external terminal in order to provide a current path from the external terminal to the another external in response to an ESD event associated with the external terminal; and

a third bipolar switching device operably coupled to the thyristor circuit, the third bipolar transistor triggering the thyristor circuit in response to a voltage of the ESD event exceeding a threshold voltage associated with the third bipolar switching device, thereby providing the current path from the external terminal to the another external terminal in order to provide a conductive path for the ESD event; wherein

the threshold voltage is independently configurable of the thyristor circuit; and the thyristor circuit, when in use, exhibits a bidirectional snapback characteristic and a snapback voltage associated therewith.

Assignments (31)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0241. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 5, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
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MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040652/0241 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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PATENT RELEASE Recorded Jan 14, 2016
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To: FREESCALE SEMICONDUCTOR, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 1, 2012
From: BESSE, PATRICE; LAINE, JEAN PHILIPPE
To: FREESCALE SEMICONDUCTOR INC
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