Providing an automatic optical inspection feature for solder joints on semiconductor packages
View Patent ↗A mechanism is provided by which optically-inspectable features formed during surface mount bonding of no-leads packages are enhanced. Embodiments of the present invention use a lead frame having features that will lie upon the edges of the finished semiconductor device package, where molding material is prevented from lying in those features through the use of a preplaced film on the lead frame or film-assisted molding in conjunction with a mold chase that conforms to the features provided on the lead frame. Embodiments use a lead frame that has a pre-plated solderable surface, such that the exposed features enhance formation of the optically-inspectable features during solder reflow operations of PCB mounting.
1. A method of making a semiconductor device package, the method comprising:
providing a lead frame comprising one or more leads having a lead feature formed in a first major surface of the one or more leads, wherein
the lead feature is exposed on side surfaces of the one or more leads, and
the first major surface is an external contact surface of the semiconductor device package;
placing the lead frame on a mold chase, wherein
the mold chase comprises one or more mold features that correspond to each lead feature of the lead frame, and
each mold feature conforms to each corresponding lead feature;
positioning a film between the one or more lead features and the corresponding mold features wherein the film conforms to each of the one or more lead features after said placing the lead frame on the mold chase;
forming an encapsulant over and around the lead frame and any other components included in the semiconductor device package; and
singulating the semiconductor device package on a plane through a portion of a lead feature.
2. The method of claim 1 further comprising:
plating the first major surface of the lead frame with a solderable metal prior to said placing the lead frame on the mold chase.
3. The method of claim 2 further comprising:
removing the film subsequent to said singulating to expose the plated first major surface of the one or more leads and the corresponding lead features.
4. The method of claim 3 further comprising:
electrically coupling the semiconductor device package to a printed circuit board, wherein said electrically coupling comprises performing a solder reflow between electrical contacts on the printed circuit board and external contact surfaces of the semiconductor device package; and
forming an optically-inspectable solder feature between an electrical contact on the printed circuit board and a lead feature during said electrically coupling.
5. The method of claim 2 wherein the solderable metal comprises one or more of tin, gold, silver, nickel, and palladium.
6. The method of claim 1 further comprising
forming the lead frame using an etching process, wherein a lead feature comprises a maximum depth less than or equal to half a thickness of a corresponding lead of the one or more leads.
7. The method of claim 6 wherein the lead feature comprises a semicircular cross sectional shape.
8. The method of claim 6 wherein the lead frame comprises copper and is plated with a solderable metal on a major surface of the one or more leads and surfaces of the corresponding lead features.
9. The method of claim 1 further comprising:
coupling a major surface of a semiconductor device die to a portion of the lead frame; and
electrically coupling an electrical contact of the semiconductor device die to one or more of the leads, wherein
the portion of the lead frame comprises a die pad, and
said forming the encapsulant further comprises forming the encapsulant over and around the semiconductor device die.
10. The method of claim 9 wherein said electrically coupling the electrical contact of the semiconductor device die to one or more of the leads comprises:
forming one or more wire bonds between the electrical contact of the semiconductor device die and the one or more leads, and
said forming the encapsulant further comprises forming the encapsulant over and around the one or more wire bonds.
11. The method of claim 1 wherein said singulating the semiconductor device package comprises:
separating the semiconductor device package from a neighboring semiconductor device package through a plane substantially perpendicular to a major surface of the semiconductor device package, wherein the plane is through one or more of the lead features on a perimeter of the semiconductor device package.
12. The method of claim 11 wherein said separating results in a solderable surface along the lead feature of each exposed lead.
13. The method of claim 1 wherein said positioning the film between the one or more lead features and the corresponding mold features comprises:
attaching a film on the first major surface of the one or more leads, wherein said placing the lead frame on the mold chase pushes the film onto a surface of the lead feature such that the film conforms to the surface of the lead feature.
14. The method of claim 1 wherein said positioning the film between the one or more lead features and the corresponding mold features comprises:
placing a film assisted molding film between the lead frame and the mold chase, wherein said placing the lead frame on the mold chase conforms the film assisted molding film to the lead frame and the mold chase.
15. A method of forming a semiconductor device package, the method comprising:
forming a lead portion of a lead frame, wherein
the lead portion comprises a top major surface and a bottom major surface,
the bottom major surface comprises a lead feature, and
the lead feature extends a width of the lead portion;
plating the lead portion of the lead frame with a solderable metal, wherein the solderable metal coats a surface of the lead feature and the bottom surface of the lead portion;
placing the lead portion of the lead frame on a mold chase, wherein a mold chase feature conforms to the lead feature;
placing a film between the bottom surface of the lead portion and the mold chase prior to said placing the lead portion of the lead frame on the mold chase, wherein the film conforms to the surface of the lead feature upon said placing the lead portion of the lead frame on the mold chase; and
forming an encapsulant over and around the lead portion of the lead frame, wherein the film prevents encapsulant from forming in the lead feature.
16. The method of claim 15 further comprising:
etching the lead feature on the lead portion, wherein the lead feature has a maximum depth less than or equal to half a thickness of the lead portion.
17. The method of claim 15 further comprising:
removing the film subsequent to said forming the encapsulant, wherein said removing exposes the plated surface of the lead feature.
18. The method of claim 15 further comprising:
cutting the encapsulant and one or more leads along a plane passing through a cross section of the lead feature.
19. The method of claim 18 wherein the plated surface of the lead feature provides a solderable surface subsequent to said cutting.
20. A method for forming a printed circuit board comprising a semiconductor device package made using the method of claim 19 , the method comprising:
forming a first solder bond between a portion of the bottom major surface of the lead portion and a contact pad on a surface of the printed circuit board; and
forming a second solder bond between at least a portion of the plated surface of the lead feature and the contact pad on the surface of the printed circuit board, wherein
the second solder bond is of a size and shape sufficient to pass an automatic optical inspection.