Memory column drowsy control
View Patent ↗In accordance with at least one embodiment, column level power control granularity is provided to control a low power state of a memory using a drowsy column control bit to control the low power state at an individual column level to protect the memory from weak bit failure. In accordance with at least one embodiment, a method of using a dedicated row of bit cells in a memory array is provided wherein each bit in the row controls the low power state of a respective column in the array. A special control signal is used to access the word line, and the word line is outside of the regular word line address space. A mechanism is provided to designate the weak bit column and set the control bit corresponding to that particular column to disable the drowsy/low power state for that column.
1. Apparatus comprising:
a memory array comprising a plurality of memory cells organized according to a plurality of rows and a plurality of columns; and
a control row comprising a plurality of power control memory cells for controlling power provided to the memory array, the plurality of power control memory cells organized according to the plurality of columns, wherein the plurality of power control memory cells store power control data to select a full voltage level for a weak column of the plurality of memory cells, wherein the weak column includes at least one weak memory cell incapable of memory retention at a reduced voltage level, and the power control memory cells store power control data to select the reduced voltage level for a normal column of the plurality of memory cells, wherein the normal column consists of normal memory cells capable of memory retention at the reduced voltage level.
2. The apparatus of claim 1 wherein a power control memory cell of the control row controls a power state of a column of the plurality of columns.
3. The apparatus of claim 1 further comprising:
a plurality of power control circuits coupled to the power control memory cells and to the memory array, the plurality of power control circuits for gating power to the memory array.
4. The apparatus of claim 1 wherein a power control memory cell of the plurality of power control memory cells stores a value that indicates a voltage provided to the memory cells corresponding to the power control memory cell.
5. The apparatus of claim 4 wherein the plurality of power control memory cells store power control data to select among the full voltage level and the reduced voltage level on a per column basis.
6. Apparatus comprising:
a memory cell for storing a stored datum, said memory cell comprising a power supply node for receiving power to operate the memory cell;
a power switch coupled to the memory cell, wherein the power switch selectively provides power to the power supply node at a first voltage level to cause the memory cell to be capable of read and write operations and at a second voltage level to cause the memory cell to enter a stored datum retention mode wherein the memory cell retains the stored datum while consuming reduced power; and
a power control circuit coupled to the memory cell, wherein the power control circuit selectively provides the power to the power supply node at the first voltage level regardless of a power control state of the power switch, wherein the power control memory cell selects a full voltage level for a weak column of a plurality of memory cells comprising the memory cell, wherein the weak column includes at least one weak memory cell incapable of memory retention at a reduced voltage level, wherein a second power control memory cell selects a reduced voltage level for a normal column of the t of memo cells, wherein the normal column consists of normal memory cells capable of memory retention at the reduced voltage level.
7. The apparatus of claim 6 wherein the second voltage level is a reduced voltage level at the power supply node.
8. The apparatus of claim 6 wherein the power control circuit comprises a regulated current source to provide the power to the power supply node at the second voltage level.
9. The apparatus of claim 8 wherein the regulated current source comprises a transistor having a first terminal, a second terminal, and a control terminal, wherein the control terminal controls a current flow between the first terminal and the second terminal, wherein the control terminal is connected to the second terminal.
10. The apparatus of claim 9 wherein the transistor is a field-effect transistor, wherein the first terminal is a drain terminal, wherein the second terminal is a source terminal, and wherein the control terminal is a gate terminal.
11. The apparatus of claim 6 further comprising:
a first plurality of memory cells in a same memory column of a memory array as the memory cell; and
a second plurality of memory cells in at least one other memory column of the memory array, the power control circuit providing the power to the memory cell and to the first plurality of memory cells but not to the second plurality of memory cells.
12. The apparatus of claim 6 further comprising:
a first plurality of memory cells in a same memory row of a memory array as the memory cell; and
a second plurality of memory cells in at least one other memory row of the memory array, the power control circuit providing the power to the memory cell and to the first plurality of memory cells but not to the second plurality of memory cells.
13. A method comprising:
storing a stored datum in a memory cell comprising a power supply node for receiving power to operate the memory cell; and
providing power to the power supply node at a first voltage level to cause the memory cell to be capable of read and write operations in response to either a power saving control signal being inactive or a power control memory cell being in a first state when the power saving control signal is active and at a second voltage level to cause the memory cell to enter a stored datum retention mode wherein the memory cell retains the stored datum while consuming reduced power in response to the power saving control signal being active and the power control memory cell being in a second state when the power saving control signal is active, wherein the power control memory cell stores a power control datum to select a reduced voltage level for a normal column of a plurality of memory cells comprising the memory cell, wherein the normal column consists of normal memory cells capable of memory retention at the reduced voltage level, wherein a second power control memory cell stores a second power control datum to select a full voltage level for a weak column of the plurality of memory cells, wherein the weak column includes at least one weak memory cell incapable of memory retention at the reduced voltage level.
14. The method of claim 13 wherein the providing the power to the power supply node comprises:
providing the power from a regulated current source to the power supply node at the second voltage level in response to the power saving control signal being active and the power control memory cell being in the second state.
15. The method of claim 14 wherein the providing the power from the regulated current source to the power supply node at the second voltage level comprises:
controlling a current flow between a first terminal of a transistor and a second terminal of the transistor using a control terminal of the transistor, wherein the control terminal is connected to the second terminal.
16. The method of claim 15 wherein the transistor is a field-effect transistor, wherein the first terminal is a drain terminal, wherein the second terminal is a source terminal, and wherein the control terminal is a gate terminal.
17. The method of claim 13 wherein the providing the power to the power supply node comprises:
providing the power at the first voltage level to the memory cell and to a first plurality of memory cells but not to a second plurality of memory cells in response to either the power saving control signal being inactive or a power control memory cell being in a first state when the power saving control signal is active, wherein the first plurality of memory cells is in a same memory column of a memory array as the memory cell and wherein the second plurality of memory cells is in at least one other memory column of the memory array.
18. The method of claim 13 wherein the providing the power to the power supply node comprises:
providing the power at the first voltage level to the memory cell and a first plurality of memory cells but not to a second plurality of memory cells in response to either the power saving control signal being inactive or a power control memory cell being in a first state when the power saving control signal is active, wherein the first plurality of memory cells in a same memory row of a memory array as the memory cell and wherein the second plurality of memory cells is in at least one other memory row of the memory array.
19. The method of claim 13 further comprising:
selecting between the first voltage level and the second voltage level according to a value, wherein the value is stored in a power control bit cell coupled to the power control circuit.