Chip-level humidity protection
An electronic apparatus includes a semiconductor substrate, a device structure supported by the semiconductor substrate, and a guard ring surrounding the device structure. The guard ring includes a plurality of conductive structures spaced apart from one another, supported by the semiconductor substrate, and coupled to a voltage source to establish an operating voltage for the guard ring.
1. An electronic apparatus comprising:
a semiconductor substrate;
a device structure supported by the semiconductor substrate;
a guard ring surrounding the device structure;
wherein the guard ring comprises a plurality of conductive structures spaced apart from one another, supported by the semiconductor substrate, and coupled to a voltage source to establish an operating voltage for the guard ring.
2. The electronic apparatus of claim 1 , wherein adjacent conductive structures of the plurality of conductive structures laterally overlap one another in a staggered arrangement.
3. The electronic apparatus of claim 1 , wherein the guard ring further comprises a conductive bridge coupling adjacent structures of the plurality of conductive structures to bias the adjacent structures at the operating voltage.
4. The electronic apparatus of claim 1 , wherein the guard ring is disposed along a periphery of the semiconductor substrate.
5. The electronic apparatus of claim 1 , wherein the device structure comprises a bond pad, and the guard ring is disposed along a periphery of the bond pad.
6. The electronic apparatus of claim 1 , wherein the voltage source is configured to provide ground potential.
7. The electronic apparatus of claim 1 , wherein each conductive structure comprises a metal layer that forms an alloy to establish an ohmic interface with the semiconductor substrate such that the guard ring is configured as an ohmic fence.
8. The electronic apparatus of claim 1 , wherein the semiconductor substrate comprises a Group III-V semiconductor material.
9. The electronic apparatus of claim 1 , wherein the device structure comprises:
a metal layer supported by the semiconductor substrate;
a first dielectric layer patterned to define the metal layer; and
a second dielectric layer disposed between the first dielectric layer and the metal layer and comprising an atomic layer deposition (ALD) film, the ALD film being disposed along an edge of the metal layer to cover a sidewall of the metal layer.
10. An electronic apparatus comprising:
a semiconductor substrate;
a circuit element supported by the semiconductor substrate;
a bond pad coupled to the circuit element and supported by the semiconductor substrate;
a first guard ring surrounding the circuit element and the bond pad, the first guard ring comprising a plurality of conductive structures spaced from one another and supported by the semiconductor substrate; and
a second guard ring extending between the circuit element and the bond pad, surrounding the bond pad, supported by the semiconductor substrate, and coupled to a voltage source to establish an operating voltage for the second guard ring.
11. The electronic apparatus of claim 10 , wherein the second guard ring comprises a plurality of conductive structures spaced apart from one another.
12. The electronic apparatus of claim 10 , wherein the plurality of conductive structures are disposed in a laterally staggered arrangement.
13. The electronic apparatus of claim 11 , wherein the first guard ring further comprises a plurality of conductive bridges coupling adjacent structures of the plurality of conductive structures to bias the adjacent structures at the operating voltage.
14. The electronic apparatus of claim 10 , wherein the second guard ring comprises a metal layer that forms an alloy with the semiconductor substrate to establish an ohmic interface with the semiconductor substrate such that the second guard ring is configured as an ohmic fence.
15. The electronic apparatus of claim 10 , further comprising:
a first dielectric layer patterned to expose the bond pad; and
a second dielectric layer disposed between the first dielectric layer and the bond pad and along an edge of the bond pad to cover a sidewall of the bond pad.
16. The electronic apparatus of claim 15 , wherein the second dielectric layer comprises an atomic layer deposition (ALD) film.
17. A method of fabricating an electronic apparatus, the method comprising:
forming a device structure of the electronic apparatus within a semiconductor substrate;
defining an edge of a first metal layer supported by the semiconductor substrate, the edge comprising a sidewall;
depositing an atomic layer deposition (ALD) dielectric film along the edge of the first metal layer to cover the sidewall of the first metal layer;
depositing a dielectric layer on the first metal layer; and
defining a second metal layer supported by the semiconductor substrate with the dielectric layer between the first and second metal layers.
18. The method of claim 17 , wherein the first metal layer is configured to form an ohmic interface with the semiconductor substrate.
19. The method of claim 17 , wherein defining the edge of the first metal layer comprises defining an Ohmic fence surrounding a periphery of the semiconductor substrate.
20. The method of claim 17 , wherein defining the edge of the first metal layer comprises defining a bond pad such that the ALD dielectric film covers a sidewall of the bond pad.