Systems and methods for controlling power in semiconductor circuits
View Patent ↗A power control circuit includes a plurality of transistors coupled between a power supply node and a gated power supply node, wherein the gate electrode of a first transistor of the plurality of transistors is coupled to receive a power control signal, wherein, in response to assertion of the power control signal, the first transistor is placed into a conductive state; a first voltage comparator, wherein, in response to assertion of the power control signal, places a second transistor of the plurality of transistors in a conductive state when a voltage on the gated voltage supply node reaches a first reference voltage; and a second voltage comparator, wherein, in response to assertion of the power control signal, places a third transistor of the plurality of transistors in a conductive state when the voltage on the gated voltage supply node reaches a second reference voltage different from the first reference voltage.
1. A power control circuit comprising:
a power supply node;
a gated voltage supply node;
a plurality of transistors coupled between the power supply node and the gated voltage supply node, each having a control electrode, a first current electrode coupled to the power supply node, and a second current electrode coupled to the gated voltage supply node, wherein the gate electrode of a first transistor of the plurality of transistors is coupled to receive a power control signal, wherein, in response to assertion of the power control signal, the first transistor is placed into a conductive state;
a first voltage comparator having a first input and having a first output coupled to the control gate of a second transistor of the plurality of transistors, wherein, in response to assertion of the power control signal, the first input is coupled to the gated voltage supply node and the first output places the second transistor in a conductive state when a voltage on the gated voltage supply node reaches a first reference voltage; and
a second voltage comparator having a second input and having a second output coupled to the control gate of a third transistor of the plurality of transistors, wherein, in response to assertion of the power control signal, the second input is coupled to the gated voltage supply node and the second output places the third transistor in a conductive state when the voltage on the gated voltage supply node reaches a second reference voltage that is different from the first reference voltage; and
a single a switch having a first terminal coupled to the gated voltage supply node, a second terminal coupled to the first input and the second input, and a control terminal coupled to receive the power control signal, wherein, in response to assertion of the power control signal, the switch couples the first input to the gated voltage supply node and the second input to the gated voltage supply node.
2. The power control circuitry of claim 1 , wherein the first reference voltage is internal to the first voltage comparator and the second reference voltage is internal to the second voltage comparator.
3. The power control circuitry of claim 1 , wherein at least two transistors of the plurality of transistors are different sizes.
4. The power control circuitry of claim 1 , wherein the second reference voltage is greater than the first reference voltage.
5. The power control circuitry of claim 1 , wherein:
the first voltage comparator comprises:
a fourth transistor having a control electrode coupled to the first input, a first current electrode, and a second current electrode coupled to the first output; and
a fifth transistor having a control electrode coupled to the first input, a first current electrode coupled to the first output, and a second current electrode; and
the second voltage comparator comprises:
a sixth transistor having a control electrode coupled to the second input, a first current electrode, and a second current electrode coupled to the second output; and
a seventh transistor having a control electrode coupled to the second input, a first current electrode coupled to the second output, and a second current electrode.
6. The power control circuitry of claim 5 , wherein a ratio of sizes between the fourth and fifth transistor determine the first reference voltage, and a ratio of sizes between the sixth and seventh transistor determine the second reference voltage.
7. The power control circuitry of claim 5 , wherein:
the first voltage comparator comprises:
an eighth transistor having a first current electrode coupled to the first current electrode of the fourth transistor, a control electrode coupled to the first output, and a second current electrode coupled to ground;
the second voltage comparator comprises:
a ninth transistor having a first current electrode coupled to the first current electrode of the sixth transistor, a control electrode coupled to the second output, and a second current electrode coupled to ground; and
a tenth transistor having a first current electrode coupled to the second current electrode of the seventh transistor, a control electrode coupled to the second output, and a second current electrode coupled to the power supply node.
8. The power control circuitry of claim 7 , wherein the sixth transistor has a same size as the fourth transistor, and the seventh transistor has a same size as the fifth transistor.
9. The power control circuitry of claim 7 , wherein the first voltage comparator comprises an eleventh transistor having a first current electrode coupled to the second current electrode of the fifth transistor, a control electrode coupled to the first output, and a second current electrode coupled to the power supply node.
10. The power control circuitry of claim 5 , wherein the fourth and fifth transistors are coupled between the power supply node and ground, and the sixth and seventh transistors are coupled between the power supply node and ground.
11. A method of powering up a gated voltage supply node, comprising:
in response to commencing power up the gated voltage supply node, placing a first transistor coupled between the gated voltage supply node and a power supply node in a conductive state, and operating a single switch to couple a first input of a first comparator and a second input of a second comparator to the gated voltage supply node;
detecting when a voltage of the gated voltage supply node reaches a first reference voltage and a second reference voltage, wherein the second reference voltage is greater than the first reference voltage;
when the voltage of the gated voltage supply node reaches the first reference voltage, placing a second transistor coupled between the gated voltage supply node and the power supply node in a conductive state; and
when the voltage of the gated voltage supply node reaches the second reference voltage, placing a third transistor coupled between the gated voltage supply node and the power supply node in a conductive state.
12. The method of claim 11 , wherein the third transistor is bigger than at least one of the first or the second transistor.
13. The method of claim 11 , wherein the detecting when a voltage of the gated voltage supply node reaches a first reference voltage is performed by a first voltage detector and the detecting when a voltage of the gated voltage supply node reaches a second reference voltage is performed by a second voltage detector, wherein the first voltage detector comprises a first inverter having a first trip point corresponding to the first reference voltage, and the second voltage detector comprises a second inverter having a second trip point corresponding to the second reference voltage.
14. The method of claim 13 , wherein each of the first and second voltage detectors is further characterized as a Schmitt trigger.
15. A power control circuit, comprising:
a first transistor having a first current electrode coupled to a power supply node, a control electrode coupled to receive a power up control signal, and a second current electrode coupled to a gated voltage supply voltage node;
a second transistor having a first current electrode coupled to the power supply node, a control electrode, and a second current electrode coupled to the gated voltage supply node;
a third transistor having a first current electrode coupled to the power supply node, a control electrode, and a second current electrode coupled to the gated voltage supply node;
a switch having a first terminal coupled to the gated voltage supply node, a second terminal, and a control terminal coupled to receive the power up control signal;
a first inverter coupled between the second terminal of the switch and the control gate of the second transistor, wherein the first inversion circuit has a first trip point; and
a second inverter coupled between the second terminal of the switch and the control gate of the third transistor, wherein the second inversion circuit has a second trip point greater than the first trip point wherein, in response to assertion of the power up control signal, the second terminal of the switch couples a first input of the first inverter to the gated voltage supply node and a second input of the second inverter to the gated voltage supply node.
16. The power control circuitry of claim 15 , wherein the third transistors is larger than at least one of the first transistor and the second transistor.
17. The power control circuitry of claim 15 , wherein:
the first inverter comprises:
a fourth transistor having a first current electrode, a control electrode coupled to the second terminal of the switch, and a second current electrode coupled to the control electrode of the second transistor;
a fifth transistor having a first current electrode coupled to the second current electrode of the fourth transistor and the control electrode of the second transistor, a control electrode coupled to the second terminal of the switch, and a second current terminal, wherein the fourth and fifth transistors are coupled between the power supply node and a ground node; and
the second inverter comprises:
a sixth transistor having a first current electrode, a control electrode coupled to the second terminal of the switch, and a second current electrode coupled to the control electrode of the third transistor; and
a seventh transistor having a first current electrode coupled to the second current electrode of the sixth transistor and the control node of the third transistor, a control electrode coupled to the second terminal of the switch, and a second current terminal, wherein the sixth and seventh transistors are coupled between the power supply node and the ground node.
18. The power circuit of claim 17 , further comprising:
an eighth transistor having a first current electrode coupled to the first current electrode of the fourth transistor, a control electrode coupled to the control electrode of the second transistor, and a second current electrode coupled to the ground node;
a ninth transistor having a first current electrode coupled to the first current electrode of the sixth transistor, a control electrode coupled to the control electrode of the third transistor, and a second current electrode coupled to the ground node; and
a tenth transistor having a first current electrode coupled to the second current electrode of the seventh transistor, a control electrode coupled to the control electrode of the third transistor, and a second current electrode coupled to the power supply node.
19. The power circuit of claim 18 , further comprising:
an eleventh transistor having a first current electrode coupled to the second current electrode of the fifth transistor, a control electrode coupled to the control electrode of the second transistor, and a second current electrode coupled to the power supply node.