Granted Patent B2

US 8,971,147 · App. 13/663,636 · Granted Mar 3, 2015

Abstract

Claims (54)

1. A memory comprising:

an array of multi-gate memory cells;

an address decoder;

a control gate word line driver circuit coupled to the address decoder and coupled to a sector of memory cells of the array, the control gate word line driver circuit is controllable to place an associated control gate word line coupled to the control gate word line driver circuit and coupled to the sector in a floating state during a read operation in at least one mode of operation where the sector is a non selected sector;

a plurality of control gate word line driver circuits including the control gate word line driver circuit, each control gate word line driver circuit of the plurality of control gate word line driver circuits is coupled to an associated sector of memory cells of the array via an associated control gate word line of a plurality of control gate word lines, during a read operation in at least a first mode of operation, each of the control gate word line driver circuits of the plurality of control gate word line driver circuits coupled to a non selected sector of the array places its associated control gate word line in a floating state and a control gate word line driver circuit of the plurality of control gate word line driver circuits coupled to a selected sector of the array applies a read voltage to its associated control gate word line of the plurality of control gate word lines;

wherein during a read operation in a second mode of operation, each of the control gate word line driver circuits of the plurality of control gate word line driver circuits coupled to a non selected sector of the array applies a read voltage to its associated control gate word line of the plurality of control gate word lines.

2. A memory comprising:

an array of multi-gate memory cells;

an address decoder;

a control gate word line driver circuit coupled to the address decoder and coupled to a sector of memory cells of the array, the control gate word line driver circuit is controllable to place an associated control gate word line coupled to the control gate word line driver circuit and coupled to the sector in a floating state during a read operation in at least one mode of operation where the sector is a non selected sector;

wherein the control gate word line driver circuit includes a P-channel transistor and an N-channel transistor, each of the P-channel transistor and the N-channel transistor is coupled to the associated control gate word line, wherein during a read in the at least one mode of operation, the P-channel transistor is non conductive, the N-channel transistor is conductive if the sector is a selected sector, and the N channel transistor is non conductive if the sector is a non selective sector.

3. The memory of claim 2 wherein during a read operation in a second mode of operation, the P-channel transistor is non conductive and the N-channel transistor is conductive whether the sector is a selected sector or non selected sector.

4. The memory of claim 2 , the control gate word line driver circuit further comprising:

a first level shifter circuit that provides a gate voltage to a gate of the N-channel transistor; and

a second level shifter circuit that provides an inverse gate voltage to a gate of the P-channel transistor.

5. A memory comprising:

an array of multi-gate memory cells;

an address decoder;

a control gate word line driver circuit coupled to the address decoder and coupled to a sector of memory cells of the array, the control gate word line driver circuit is controllable to place an associated control gate word line coupled to the control gate word line driver circuit and coupled to the sector in a floating state during a read operation in at least one mode of operation where the sector is a non selected sector;

wherein during the at least one mode of operation, the control gate word line driver circuit places the associated control gate word line in a floating state when no access operations are being performed to the array.

6. The memory of claim 5 further comprising:

a voltage regulator to provide a read voltage when enabled to the control gate word line driver circuit during a read of memory cells of the sector, wherein during the at least one mode of operation, the voltage regulator is not enabled when no access operations are being performed to the array.

7. The memory of claim 6 , wherein during a read during the at least one mode of operation, the voltage regulator transitions from a non enabled state to an enabled state with a selected control gate word line of a plurality of control gate word lines of the memory receiving power from the voltage regulator and no non selected control gate word lines of the plurality of control gate word lines receiving power from the voltage regulator.

8. The memory of claim 5 wherein during a second mode of operation, the control gate word line driver circuit applies a read voltage to the associated control gate word line when no access operations are being performed to the array.

9. The memory of claim 5 further comprising:

a plurality of control gate word line driver circuits including the control gate word line driver circuit, each control gate word line driver circuit of the plurality of control gate word line driver circuits is coupled to an associated sector of memory cells of the array via an associated control gate word line of a plurality of control gate word lines, during a read operation in at least a first mode of operation, every control gate word line driver circuit of the plurality of control gate word line driver circuits coupled to a non selected sector of the array places its associated control gate word line in a floating state and a control gate word line driver circuit of the plurality of control gate word line driver circuits coupled to a selected sector of the array applies a read voltage to its associated control gate word line of the plurality of control gate word lines.

10. A method comprising:

during a read operation to cells of an array of multi-gate memory cells of a memory, operating control gate word lines associated with non selected sectors of a plurality of sectors of the array in a floating state, the control gate word lines are of a plurality of control gate word lines, each of the plurality of control gate word lines is associated with a sector of the plurality of sectors;

concurrently with the operating, applying a read voltage to a control gate word line associated with a selected sector of the plurality of sectors of the array, the selected sector including memory cells being read during the read operation, the control gate word line associated with the selected sector being a control gate word line of the plurality of control gate word lines;

wherein the operating and applying are performed during a first mode of operation;

during a second read operation in a second mode of operation, applying a read voltage to the control gate word lines of the plurality of control gate word lines associated with selected and non selected sectors of the plurality of sectors of the array.

11. A method comprising:

during a read operation to cells of an array of multi-gate memory cells of a memory, operating control gate word lines associated with non selected sectors of a plurality of sectors of the array in a floating state, the control gate word lines are of a plurality of control gate word lines, each of the plurality of control gate word lines is associated with a sector of the plurality of sectors;

concurrently with the operating, applying a read voltage to a control gate word line associated with a selected sector of the plurality of sectors of the array, the selected sector including memory cells being read during the read operation, the control gate word line associated with the selected sector being a control gate word line of the plurality of control gate word lines;

wherein during at least a first mode of operation, operating the control gate word lines of the plurality of control gate word lines in a floating state when no access operations are being performed to the array.

12. The method of claim 11 , wherein during a second mode of operation, applying a read voltage to the control gate word lines of the plurality of control gate word lines when no access operations are being performed to the array.

13. A method comprising:

during a read operation to cells of an array of multi-gate memory cells of a memory, operating control gate word lines associated with non selected sectors of a plurality of sectors of the array in a floating state, the control gate word lines are of a plurality of control gate word lines, each of the plurality of control gate word lines is associated with a sector of the plurality of sectors;

concurrently with the operating, applying a read voltage to a control gate word line associated with a selected sector of the plurality of sectors of the array, the selected sector including memory cells being read during the read operation, the control gate word line associated with the selected sector being a control gate word line of the plurality of control gate word lines;

wherein the read voltage is supplied by a voltage regulator, wherein prior to the read operation, the voltage regulator is disabled, power is supplied to at least some devices of the memory, and the plurality of control gate word lines are in a floating state;

wherein as part of the read operation, the voltage regulator is enabled while supplying power to the control gate word line associated with the selected sector of the plurality of sectors of the array and the voltage regulator does not supply power to the control gate word lines associated with non selected sectors.

14. A memory comprising:

an array of multi-gate memory cells arranged in a plurality of sectors, each memory cell of the array including a control gate;

a plurality of control gate word lines, each of the plurality of control gate word lines is coupled to an associated sector of the plurality of sectors;

a plurality of driver circuits, each of the plurality of driver circuits is coupled to an associated control gate word line of the plurality of control gate word lines, wherein during a read operation in at least one mode of operation, the plurality of driver circuits operate non selected control gate word lines of the plurality of control gate word lines in a floating state and apply a read voltage to a control gate word line of the plurality of control gate word lines associated with a selected sector of the plurality of sectors;

wherein during a second mode of operation, the plurality of driver circuits apply a read voltage to control gate word lines of the plurality of control gate word lines associated with selected and non selected sectors of the plurality of sectors.

15. A memory comprising:

an array of multi-gate memory cells arranged in a plurality of sectors, each memory cell of the array including a control gate;

a plurality of control gate word lines, each of the plurality of control gate word lines is coupled to an associated sector of the plurality of sectors;

a plurality of driver circuits, each of the plurality of driver circuits is coupled to an associated control gate word line of the plurality of control gate word lines, wherein during a read operation in at least one mode of operation, the plurality of driver circuits operate non selected control gate word lines of the plurality of control gate word lines in a floating state and apply a read voltage to a control gate word line of the plurality of control gate word lines associated with a selected sector of the plurality of sectors;

wherein each driver circuit of the plurality of driver circuits includes a stack of transistors including and N-channel transistor and a P-channel transistor, wherein when a driver circuit of the plurality of driver circuits places its associative control gate word line in a floating state, the N-channel transistor and P-channel transistor are each placed in a non conductive state.

16. The memory of claim 15 , wherein when a driver circuit of the plurality of driver circuits applies a read voltage its associated control gate word line, the N-channel transistor is placed in a conductive state.

17. The memory of claim 5 wherein the multi-gate memory cells of the array are characterized as split gate memory cells.

18. The memory of claim 14 wherein the multi-gate memory cells of the array are characterized as split gate memory cells.

Assignments (21)