IP Library Patent Application 13681401
Patent Application
App. No. 13/681,401

SEMICONDUCTOR WAFER DICING METHOD

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Patent No.
US None
App. No.
13/681,401
Abstract

A method of producing semiconductor dies includes providing a semiconductor wafer having front and back faces and an array of integrated circuits fabricated on it. The integrated circuits having active faces at the front face of the wafer. Grooves are cut mechanically from the back face partially through the wafer along saw streets between the integrated circuits. The integrated circuits are then singulated by scanning a laser beam on the front face within and along the saw streets, which scribes the wafer from the front face, and then singulating the integrated circuits by mechanically cleaving the wafer along the saw streets.

Claims (27)

1 . A method of separating semiconductor dies formed on a wafer, comprising:

providing a semiconductor wafer having front and back faces and an array of semiconductor dies fabricated therein, said semiconductor dies having active faces at said front face of said wafer;

mechanically cutting grooves from said wafer back face partially through said wafer along saw streets between said semiconductor dies; and

singulating said semiconductor dies, including scanning a laser beam on said wafer front face within and along said saw streets.

2 . The method of claim 1 , wherein scanning said laser beam scribes said wafer from said front face and singulating said semiconductor dies includes loading said wafer mechanically to cleave said wafer along said saw streets.

3 . The method of claim 2 , wherein singulating said semiconductor dies includes mounting said wafer with said back face attached to a back face adhesive support element after cutting said grooves.

4 . The method of claim 3 , wherein loading said wafer mechanically includes stretching said back face adhesive support element radially to apply a radial tensile stress to said back face.

5 . The method of claim 1 , wherein said wafer includes alignment marks on said front face, said alignment marks guiding said scanning of said laser beam.

6 . The method of claim 1 , wherein said laser beam alters the structure of said wafer over a width less than and included within the width of said grooves.

7 . The method of claim 1 , wherein said laser beam is pulsed and scans each of said saw streets in a plurality of scans focused at respective depths in said wafer.

8 . The method of claim 1 , further comprising back-grinding said wafer to produce said back face.

9 . The method of claim 1 , wherein cutting said grooves includes mounting said wafer with said front face attached to a front face support element and sawing partially through said wafer from said back face.

10 . The method of claim 9 , wherein said wafer includes alignment marks on said front face, said alignment marks being sensed through said front face support element and guiding said sawing partially through said wafer from said back face.

11 . The method of claim 10 , wherein said alignment marks on said front face guide said scanning of said laser beam.

12 . A method of producing semiconductor devices, comprising:

providing a semiconductor wafer having front and back faces and an array of semiconductor dies fabricated therein, said semiconductor dies having active faces at said front face of said wafer;

mechanically cutting grooves from said wafer back face partially through said wafer along saw streets between said semiconductor dies;

singulating said semiconductor dies, including scanning a laser beam on said wafer front face within and along said saw streets, wherein said singulated semiconductor dies have edges and said grooves form undercuts in said edges under said active faces, and said active faces have widths greater than said back faces;

providing die support members having support surfaces; and

attaching said back faces of said semiconductor dies to said support surfaces with a die attach material, wherein the die attach material flows into said undercut and a fillet is formed in said undercut.

13 . The method of claim 12 , wherein scanning said laser beam scribes said wafer from said front face and singulating said semiconductor dies includes loading said wafer mechanically to cleave said wafer along said saw streets.

14 . The method of claim 13 , wherein singulating said semiconductor dies includes mounting said wafer with said back face attached to a back face adhesive support element after cutting said grooves.

15 . The method of claim 14 , wherein loading said wafer mechanically includes stretching said back face adhesive support element radially to apply a radial tensile stress to said back face.

16 . The method of claim 12 , wherein said laser beam alters the structure of said wafer over a width less than and included within the width of said grooves.

17 . The method of claim 12 , wherein said laser beam is pulsed and scans each of said saw streets in a plurality of scans focused at respective depths in said wafer.

18 . The method of claim 12 , further comprising back-grinding said wafer to produce said back face.

19 . The method of claim 12 , wherein cutting said grooves includes mounting said wafer with said front face attached to a front face support element and sawing partially through said wafer from said back face.

Assignments (18)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
PATENT RELEASE Recorded Jan 14, 2016
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037494/0312 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0671 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0685 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Apr 22, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030258/0558 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Apr 22, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 030258/0540 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Apr 22, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030258/0523 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 20, 2012
From: QIU, SHUNAN; GONG, GUOLIANG; LI, JUN; LIU, HAIYAN
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 029324/0750 →