Reducing the power consumption of memory devices
View Patent ↗Systems and methods for reducing the power consumption of memory devices. A method of operating a memory device may include monitoring a plurality of sense amplifiers, each sense amplifier configured to evaluate a logic value stored in a memory cell, determining whether each of the plurality of sense amplifiers has completed its evaluation, and stopping a reference current from being provided to the sense amplifiers in response to all of the sense amplifiers having completed their evaluations. An electronic circuit may include memory cells, sense amplifiers coupled to the memory cells, transition detection circuits coupled to the sense amplifiers, and control circuitry coupled to the transition detection circuits, the transition detection circuits configured to stop a reference current from being provided to the sense amplifiers if each transition detection circuit determines that its respective sense amplifier has identified a logic value stored in a respective memory cell.
1. A method of operating a memory, the method comprising:
monitoring a plurality of sense amplifiers, each of the plurality of sense amplifiers configured to evaluate a logic value stored in a respective memory cell based upon a comparison between a reference current and the respective memory cell's output current;
determining whether each of the plurality of sense amplifiers has completed its evaluation based upon the monitoring; and
stopping the reference current from being provided to the plurality of sense amplifiers in response to all of the plurality of sense amplifiers having completed their evaluations.
2. The method of claim 1 , wherein during the monitoring the reference current is applied to each of the plurality of sense amplifiers if fewer than all of the plurality of sense amplifiers have completed their evaluations.
3. The method of claim 1 , wherein monitoring the plurality of sense amplifiers includes monitoring, for each of the plurality of sense amplifiers, a first node and a second node.
4. The method of claim 3 , wherein the first node is configured to receive the reference current and the second node is configured to receive a memory cell's output current.
5. The method of claim 4 , the monitoring further comprising, for each of the plurality of sense amplifiers, comparing a voltage at the first node against another voltage at the second node.
6. The method of claim 1 , further comprising, for a given one the plurality of sense amplifiers, generating an indication that the given sense amplifier has evaluated the logic value stored in its respective memory cell.
7. The method of claim 1 , further comprising stopping the reference current from being provided after a predetermined amount of time following a determination that each of the plurality of sense amplifiers has completed its evaluation.
8. An electronic circuit, comprising:
a plurality of memory cells;
a plurality of sense amplifiers, each of the plurality of sense amplifiers operably coupled to one or more of the plurality of memory cells;
a plurality of transition detection circuits, each transition detection circuit operably coupled to a respective one of the plurality of sense amplifiers; and
control circuitry operably coupled to the plurality of transition detection circuits and configured to stop a reference current from being provided to the plurality of sense amplifiers in response to each of the plurality of transition detection circuits having made a determination that its respective one of the plurality of sense amplifiers has identified a logic value stored in one of the plurality of memory cells.
9. The electronic circuit of claim 8 , the control circuitry further configured to provide the reference current to the plurality of sense amplifiers in response to fewer than all of the plurality of transition detection circuits having made the determination.
10. The electronic circuit of claim 8 , each of the plurality of transition detection circuits configured to monitor, for its respective sense amplifier, a first output of a first node and a second output of a second node.
11. The electronic circuit of claim 10 , each of the plurality of transition detection circuits further comprising a first logic circuit configured to output a predetermined value in response to the first and second outputs having different logic values.
12. The electronic circuit of claim 11 , the first logic circuit comprising: (a) logic circuitry configured to implement an exclusive OR (XOR) operation, the logic circuitry having its inputs operably coupled to the first and second nodes of the respective sense amplifier, and (b) a flip-flop having one of its inputs operably coupled to an output of the logic circuitry and another of its inputs configured to receive a reset signal.
13. The electronic circuit of claim 12 , further comprising a buffer circuit operably coupled to the first and second nodes of the respective sense amplifier and to inputs of the logic circuitry.
14. The electronic circuit of claim 11 , the control circuitry further comprising a second logic circuit configured to output a control signal in response to all of the plurality of transition detection circuits outputting the predetermined value.
15. The electronic circuit of claim 14 , the second logic circuit comprising: (a) first logic circuitry configured to implement a NAND operation, the first logic circuitry having its inputs operably coupled to the outputs of the first logic circuit, and (b) second logic circuitry configured to implement an AND operation, the second logic circuitry having: one of its inputs operably coupled to an output of the first logic circuitry, another of its inputs configured to receive a clock signal, and its output configured to provide a reference current enabling signal.
16. The electronic circuit of claim 8 , further comprising a reference current generation circuit operably coupled to the control circuitry and to the plurality of sense amplifiers, the reference current generation circuit configured to output the reference current to each of the plurality of sense amplifiers in the absence of an indication from the control circuitry.