LDMOS device with minority carrier shunt region
View Patent ↗A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and having a first conductivity type, a gate structure supported by the semiconductor substrate between the source and drain regions, a well region in the semiconductor substrate, having a second conductivity type, and in which a channel region is formed under the gate structure during operation, and a shunt region adjacent the well region in the semiconductor substrate and having the second conductivity type. The shunt region has a higher dopant concentration than the well region to establish a shunt path for charge carriers of the second conductivity type that electrically couples the well region to a potential of the source region.
1. A device comprising:
a semiconductor substrate;
source and drain regions in the semiconductor substrate and having a first conductivity type;
a gate structure supported by the semiconductor substrate between the source and drain regions;
a well region in the semiconductor substrate, having a second conductivity type, and in which a channel region is formed under the gate structure during operation; and
a shunt region adjacent the well region in the semiconductor substrate and having the second conductivity type;
wherein the shunt region has a higher dopant concentration than the well region to establish a shunt path for charge carriers of the second conductivity type that electrically couples the well region to a potential of the source region.
2. The device of claim 1 , wherein the shunt region has a bottom deeper than a bottom of the well region.
3. The device of claim 1 , wherein the shunt region is disposed under the source region such that the shunt path extends under the source region.
4. The device of claim 1 , wherein the shunt region does not extend under the gate structure.
5. The device of claim 1 , wherein the shunt region is aligned with a source-side of the gate structure.
6. The device of claim 1 , wherein the shunt region is spaced from a source-side corner of the gate structure.
7. The device of claim 1 , further comprising:
a contact disposed on a backside of the semiconductor substrate; and
a sinker region in the semiconductor substrate, having the second conductivity type, and configured to establish an electrical connection between the source region and the backside contact;
wherein the shunt region is adjacent the sinker region such that the shunt path is electrically coupled to the backside contact.
8. The device of claim 1 , wherein the shunt region is laterally spaced from a source-side edge of the gate structure.
9. The device of claim 1 , wherein the shunt path is laterally oriented.
10. The device of claim 1 , wherein the shunt region is configured to lower an effective base resistance of a parasitic bipolar transistor having the well region as a base region.
11. The device of claim 1 , further comprising a drift region in the semiconductor substrate between the well region and the drain region and having the first conductivity type to allow charge carriers of the first conductivity type in the channel region to reach the drain region.
12. An electronic apparatus comprising:
a substrate; and
a transistor disposed in the substrate, the transistor comprising:
first and second semiconductor regions having a first conductivity type;
a third semiconductor region having a second conductivity type and in which a channel region is formed between the first and second semiconductor regions during operation;
a fourth semiconductor region having the second conductivity type;
wherein the fourth semiconductor region has a higher dopant concentration than the third semiconductor region to establish a shunt path for charge carriers of the second conductivity type, and wherein the shunt path electrically couples the third semiconductor region to a potential of the first semiconductor region.
13. The electronic apparatus of claim 12 , wherein the fourth semiconductor region has a bottom deeper than a bottom of the third semiconductor region.
14. The electronic apparatus of claim 12 , wherein the fourth semiconductor region does not extend under the channel region.
15. The electronic apparatus of claim 12 , wherein the fourth semiconductor region extends under the first semiconductor region such that the shunt path extends under the first semiconductor region.
16. A method of fabricating a transistor, the method comprising:
forming a gate structure of the transistor on a semiconductor substrate;
forming a well region in the semiconductor substrate, the well region extending under the gate structure via lateral diffusion where a channel region is formed during operation;
forming a shunt region in the semiconductor substrate adjacent the well region; and
forming a source region in the semiconductor substrate such that the shunt region is under the source region;
wherein the shunt region has a higher dopant concentration than the well region to establish a shunt path that electrically couples the well region to a potential of the source region.
17. The method of claim 16 , wherein forming the shunt region comprises conducting an implantation of dopant, and driving the dopant such that the shunt region has a bottom deeper than a bottom of the well region.
18. The method of claim 16 , wherein forming the shunt region comprises conducting an implantation of dopant that uses the gate structure as a mask.
19. The method of claim 18 , further comprising depositing a spacer along a source-side sidewall of the gate structure such that a vertical boundary of the shunt region is laterally spaced from the source-side sidewall.
20. The method of claim 18 , wherein the implantation of dopant is conducted at an angle with respect to vertical to laterally space the shunt region from a source-side corner of the gate structure.