IP Library Granted Patent US 8,637,393
Granted Patent B1
US 8,637,393 · App. 13/661,377 · Granted Jan 28, 2014

Methods and structures for capping a structure with a protective coating

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Quick Facts
Patent No.
US 8,637,393
App. No.
13/661,377
Granted
Jan 28, 2014
Kind
B1
Abstract

A surface is placed into a deposition chamber. A tin layer is formed on the surface, in which forming the tin layer includes providing a precursor into the deposition chamber for a first time period, wherein the precursor comprises one of tetrakis (dimethylamino) tin (TDMASn) or tin tetrachloride (SnCl 4 ), providing an inert gas into the deposition chamber for a second time period, providing a hydrogen reactant into the deposition chamber for a third time period, and providing the inert gas into the deposition chamber for a fourth time period. The first, second, third, and fourth time periods form one atomic layer deposition (ALD) cycle. The surface may be an exposed surface of a lead free metal.

Claims (36)

1. A method for forming tin on a surface, the method comprising:

placing the surface into a deposition chamber;

forming a tin layer on the surface, wherein the forming the tin layer comprises:

providing a precursor into the deposition chamber for a first time period, wherein the precursor comprises one of tetrakis (dimethylamino) tin (TDMASn) or tin tetrachloride (SnCl 4 );

after providing the precursor for the first time period, providing an inert gas into the deposition chamber for a second time period;

after providing the inert gas for the second time period, providing a hydrogen reactant into the deposition chamber for a third time period; and

after providing the hydrogen reactant for the third time period, providing the inert gas into the deposition chamber for a fourth time period.

2. The method of claim 1 , wherein the first, second, third, and fourth time periods form one atomic layer deposition (ALD) cycle.

3. The method of claim 2 , wherein the forming the tin layer further comprises:

repeating the forming the tin layer until the tin layer reaches a target thickness.

4. The method of claim 3 , wherein the target thickness is in a range of 5 to 200 Angstroms.

5. The method of claim 1 , wherein the surface is characterized as an exposed surface of a semiconductor substrate.

6. The method of claim 1 , wherein the surface is characterized as an exposed surface of a lead-free metal layer.

7. The method of claim 1 , wherein the surface is characterized as an exposed surface of a lead-free solder sphere.

8. The method of claim 1 , further comprising:

after the forming the tin layer, performing an anneal of the tin layer.

9. The method of claim 8 , further comprising:

prior to the forming the tin layer, performing a moisture removal bake on the surface.

10. The method of claim 1 , wherein the tin layer is devoid of oxide.

11. A method for forming tin on solder spheres of a ball grid array (BGA) device, the method comprising:

placing the BGA device into a deposition chamber;

forming a tin layer on the solder spheres, wherein the forming the tin layer comprises:

providing a precursor into the deposition chamber for a first time period, wherein the precursor comprises one of tetrakis (dimethylamino) tin (TDMASn) or tin tetrachloride (SnCl 4 );

after providing the precursor for the first time period, providing an inert gas into the deposition chamber for a second time period;

after providing the inert gas for the second time period, providing a hydrogen reactant into the deposition chamber for a third time period; and

after providing the hydrogen reactant for the third time period, providing the inert gas into the deposition chamber for a fourth time period.

12. The method of claim 11 , wherein the solder spheres of the BGA device are characterized as lead free.

13. The method of claim 12 , wherein the solder spheres comprise an alloy of tin, silver, and copper.

14. The method of claim 11 , wherein the first, second, third, and fourth time periods form one atomic layer deposition (ALD) cycle.

15. The method of claim 11 , wherein the forming the tin layer on the solder spheres further comprises:

repeating the steps of providing until the tin layer reaches a target thickness.

16. The method of claim 15 , wherein the target thickness is in a range of 5 to 200 Angstroms.

17. The method of claim 11 , further comprising:

after the forming the tin layer, performing an anneal of the BGA device.

18. The method of claim 11 , further comprising:

prior to the forming the tin layer, performing a moisture removal bake on the BGA device.

Assignments (21)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
MERGER Recorded Jan 3, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041144/0363 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
PATENT RELEASE Recorded Jan 14, 2016
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To: FREESCALE SEMICONDUCTOR, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0671 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0685 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Apr 22, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Apr 22, 2013
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To: CITIBANK, N.A., AS COLLATERAL AGENT
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Apr 22, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 26, 2012
From: HEGDE, RAMA I.
To: FREESCALE SEMICONDUCTOR, INC.
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