IP Library Granted Patent US 9,704,853
Granted Patent B2
US 9,704,853 · App. 13/671,506 · Granted Jul 11, 2017

Semiconductor device and driver circuit with an active device and isolation structure interconnected through a resistor circuit, and method of manufacture thereof

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Quick Facts
Patent No.
US 9,704,853
App. No.
13/671,506
Granted
Jul 11, 2017
Kind
B2
Abstract

Embodiments of semiconductor devices and driver circuits include a semiconductor substrate having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within a portion of the substrate contained by the isolation structure, and a resistor circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a body region, which is separated from the isolation structure by a portion of the semiconductor substrate having the first conductivity type. The resistor circuit is connected between the isolation structure and the body region. The resistor circuit may include one or more resistor networks and, optionally, a Schottky diode and/or one or more PN diode(s) in series and/or parallel with the resistor network(s).

Claims (85)

1. A semiconductor device, comprising:

a semiconductor substrate having a first conductivity type and a top substrate surface;

a buried layer below the top substrate surface, wherein the buried layer has a second conductivity type that is different from the first conductivity type;

a sinker region between the top substrate surface and the buried layer, wherein the sinker region has the second conductivity type, and an isolation structure that isolates a portion of the substrate from a remainder of the semiconductor substrate is formed by the sinker region and the buried layer;

an active device in the semiconductor substrate within the portion of the substrate contained by the isolation structure, wherein the active device includes

a drift region of the first conductivity type within a central portion of the active area and extending from the top substrate surface into the semiconductor substrate,

a drain region of the first conductivity type, wherein the drain region extends into the drift region from the top substrate surface, and

a body region of the second conductivity type extending from the top substrate surface into the semiconductor substrate and positioned between the drift region and the isolation structure, wherein the body region and the isolation structure are separated by a portion of the semiconductor substrate having the first conductivity type; and

a resistor circuit having a first terminal connected to the isolation structure and a second terminal connected to the body region.

2. The semiconductor device of claim 1 , wherein the resistor circuit comprises:

a polycrystalline silicon resistor.

3. The semiconductor device of claim 1 , wherein the resistor circuit comprises:

a first resistive network; and

a Schottky diode coupled to the first resistive network, wherein the Schottky diode is formed from a Schottky contact coupled with the isolation region.

4. The semiconductor device of claim 3 , wherein:

the Schottky diode is coupled to the first resistive network in series.

5. The semiconductor device of claim 3 , wherein:

the Schottky diode is coupled to the first resistive network in parallel.

6. The semiconductor device of claim 5 , wherein the resistor circuit further comprises:

a second resistive network coupled to the Schottky diode in series.

7. The semiconductor device of claim 3 , wherein the resistor circuit further comprises:

a PN junction diode coupled to the Schottky diode in parallel.

8. The semiconductor device of claim 1 , wherein the resistor circuit comprises:

a first resistive network; and

a PN junction diode coupled to the first resistive network.

9. The semiconductor device of claim 8 , wherein:

the PN junction diode is coupled to the first resistive network in series.

10. The semiconductor device of claim 8 , wherein:

the PN junction diode is coupled to the first resistive network in parallel.

11. The semiconductor device of claim 10 , wherein the resistor circuit further comprises:

a second resistive network coupled to the PN junction diode in series.

12. The semiconductor device of claim 8 , further comprising:

a further region of the first conductivity type extending into the sinker region, wherein the PN junction diode is formed between the further region and the sinker region.

13. The semiconductor device of claim 8 , wherein the PN junction diode comprises a polycrystalline silicon diode.

14. The semiconductor device of claim 1 , wherein the active device comprises:

a drift region of the first conductivity type within a central portion of the active area and extending from the top substrate surface into the semiconductor substrate;

a drain region of the first conductivity type extending into the drift region from the top substrate surface;

the body region extending from the top substrate surface into the semiconductor substrate between the drift region and the isolation structure; and

a source region of the first conductivity type extending into the body region from the top substrate surface.

15. A driver circuit comprising:

a first laterally diffused metal oxide semiconductor field effect transistor (LDMOSFET) formed on a semiconductor substrate having a first conductivity type and a top substrate surface, wherein the first LDMOSFET includes

a buried layer below the top substrate surface, wherein the buried layer has a second conductivity type that is different from the first conductivity type,

a sinker region between the top substrate surface and the buried layer, wherein the sinker region has the second conductivity type, and an isolation structure that isolates a portion of the substrate from a remainder of the semiconductor substrate is formed by the sinker region and the buried layer,

an active device in the semiconductor substrate within the portion of the substrate contained by the isolation structure, wherein the active device includes

a drift region of the first conductivity type within a central portion of the active area and extending from the top substrate surface into the semiconductor substrate,

a drain region of the first conductivity type, wherein the drain region extends into the drift region from the top substrate surface, and

a body region of the second conductivity type extending from the top substrate surface into the semiconductor substrate and positioned between the drift region and the isolation structure, wherein the body region and the isolation structure are separated by a portion of the semiconductor substrate having the first conductivity type; and

a resistor circuit having a first terminal connected to the isolation structure and a second terminal connected to the body region.

16. The driver circuit of claim 15 , wherein the resistor circuit comprises:

a polycrystalline silicon resistor.

17. The driver circuit of claim 15 , wherein the resistor circuit comprises:

a first resistive network; and

a Schottky diode coupled to the first resistive network, wherein the Schottky diode is formed from a Schottky contact coupled with the isolation region.

18. The driver circuit of claim 17 , wherein the Schottky diode is coupled to the first resistive network in parallel, and the resistor circuit further comprises:

a second resistive network coupled to the Schottky diode in series.

19. The driver circuit of claim 15 , wherein the resistor circuit comprises:

a first resistive network; and

a PN junction diode coupled to the resistive network.

20. The driver circuit of claim 19 , further comprising:

a further region of the first conductivity type extending into the sinker region, wherein the PN junction diode is formed between the further region and the sinker region.

21. The driver circuit of claim 19 , wherein the PN junction diode comprises a polycrystalline silicon diode.

22. The driver circuit of claim 19 , wherein the PN junction diode is coupled to the first resistive network in parallel, and the resistor circuit further comprises:

a second resistive network coupled to the PN junction diode in series.

23. A method for forming a semiconductor device, the method comprising the steps of:

forming a buried layer below a top substrate surface of a semiconductor substrate having a first conductivity type, wherein the buried layer has a second conductivity type that is different from the first conductivity type;

forming a sinker region between the top substrate surface and the buried layer, wherein the sinker region has the second conductivity type, and an isolation structure that isolates a portion of the substrate from a remainder of the semiconductor substrate is formed by the sinker region and the buried layer;

forming an active device in the portion of the semiconductor substrate contained by the isolation structure, wherein the active device includes

a drift region of the first conductivity type within a central portion of the active area and extending from the top substrate surface into the semiconductor substrate,

a drain region of the first conductivity type, wherein the drain region extends into the drift region from the top substrate surface, and

a body region of the second conductivity type extending from the top substrate surface into the semiconductor substrate and positioned between the drift region and the isolation structure, wherein the body region and the isolation structure are separated by a portion of the semiconductor substrate having the first conductivity type; and

connecting a first terminal of a resistor circuit to the isolation structure, and connecting a second terminal of the resistor circuit to the body region.

24. The method of claim 23 , wherein forming the resistor circuit comprises:

forming and interconnecting a polycrystalline silicon resistor as part of the resistor circuit.

25. The method of claim 23 , wherein the resistor circuit includes a resistive network and a Schottky diode, and forming the resistor circuit comprises:

forming the resistive network;

forming the Schottky diode, wherein the Schottky diode includes a Schottky contact coupled with the isolation region; and

coupling the resistive network to the Schottky contact.

26. The method of claim 23 , wherein the resistor circuit includes a resistive network and a PN junction diode, and forming the resistor circuit comprises:

forming the resistive network;

forming a further region of the first conductivity type extending into the sinker region, wherein the PN junction diode is formed between the further region and the sinker region; and

coupling the resistive network to the further region.

27. The method of claim 23 , wherein the resistor circuit includes a resistive network and a PN junction diode, and forming the resistor circuit comprises:

forming the resistive network;

forming the PN junction diode as a polycrystalline silicon diode; and

coupling the resistive network to the polycrystalline silicon diode.

Assignments (28)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
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From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
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SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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PATENT RELEASE Recorded Jan 14, 2016
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
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PATENT RELEASE Recorded Dec 21, 2015
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PATENT RELEASE Recorded Dec 21, 2015
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SECURITY AGREEMENT Recorded Nov 6, 2013
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To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 7, 2012
From: BODE, HUBERT M.; CHEN, WEIZE; DE SOUZA, RICHARD J.; PARRIS, PATRICE M.
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