Latent slow bit detection for non-volatile memory
View Patent ↗In accordance with at least one embodiment, a non-volatile memory (NVM) and method is disclosed for detecting latent slow erase bits. At least a portion of an array of NVM cells is erased with a reduced erase bias. The reduced erase bias has a reduced level relative to a normal erase bias. A least erased bit (LEB) threshold voltage level of the least erased bit (LEB) is determined. An erase verify is performed at an adjusted erase verify read threshold voltage level. The adjusted erase verify read threshold voltage level is a predetermined amount lower than the LEB read threshold voltage level. A number of failing bits is determined. The failing bits are bits with a threshold voltage above the adjusted erase verify level. The NVM is rejected in response to the number of failing bits being less than a failing bits threshold.
1. A method for detecting a latent slow erase bit in a non-volatile memory (NVM) comprising:
erasing a plurality of the NVM cells of the NVM;
determining a least erased bit (LEB) threshold voltage level of a least erased bit (LEB) of the plurality of the NVM cells of the NVM;
performing an erase verify of the NVM at a reduced erase verify read threshold voltage level, the reduced erase verify read threshold voltage level being a predetermined amount lower than the LEB read threshold voltage level;
determining a number of failing bits, wherein failing bits are bits failing the erase verify; and
rejecting the NVM in response to the number of failing bits being less than a failing bits threshold.
2. The method of claim 1 wherein the erasing the plurality of the NVM cells comprises:
erasing the plurality of the NVM cells with a reduced erase bias and a normal erase verify level, wherein the method further comprises:
erasing the plurality of NVM cells of the NVM with a normal erase bias and the normal erase verify level, the reduced erase bias having a reduced level relative to the normal erase bias.
3. The method of claim 2 wherein the erasing the plurality of the NVM cells with the reduced erase bias comprises:
erasing the at least the portion of the NVM with a reduced substrate voltage.
4. The method of claim 2 wherein the erasing the plurality of the NVM cells with the reduced erase bias comprises:
erasing the at least the portion of the NVM with a reduced gate voltage.
5. The method of claim 1 wherein the performing the erase verify at the reduced erase verify read threshold level is performed with the reduced erase verify read threshold level being at least 100 millivolts lower than the LEB read threshold voltage level.
6. The method of claim 1 wherein the performing the erase verify at the reduced erase verify read threshold level is performed with the reduced erase verify read threshold level being at least 200 millivolts but not more than 700 millivolts lower than the LEB read threshold voltage level.
7. The method of claim 1 wherein the performing the erase verify at the reduced erase verify read threshold level comprises:
adjusting a charge pump to obtain a lower voltage in burn-in cycling to detect intermittent slow erase bits.
8. A method for detecting a latent slow bit in a non-volatile memory (NVM) comprising:
performing program/erase cycling of the NVM in production test flow;
performing the method of claim 1 at each readout cycle during the cycling.
9. The method of claim 8 wherein erasing during a non-readout program/erase cycle of the program/erase cycling is performed using a normal erase bias and a normal erase verify read threshold voltage level.
10. A method for detecting a latent slow bit in a non-volatile memory (NVM) comprising:
altering a storage state of the plurality of bits of the NVM;
determining a last changed bit threshold voltage level of a last changed bit of the plurality of bits, wherein the last changed bit of the plurality of bits is a bits whose storage state is changed last by the altering the storage state of the plurality of bits;
performing a state change verification of the bits using an adjusted state change verification voltage level, the adjusted state change verification voltage level imposing a more stringent threshold voltage for verifying an altered storage state of a bit of the plurality of bits than the last changed bit threshold voltage level;
comparing a number of failing bits which failed the state change verification to a failing bits threshold; and
rejecting a device comprising the NVM in response to the number of failing bits being fewer than the failing bits threshold.
11. The method of claim 10 wherein the altering the storage state of the plurality of bits of the NVM comprises:
altering the storage state of the plurality of bits of the NVM using a reduced bias voltage level and a normal state change verification voltage level, wherein the method further comprises:
altering the storage state of the plurality of bits of the NVM using a normal bias voltage level and the normal state change verification voltage level, wherein the reduced bias voltage level is less potent than the normal bias voltage level.
12. The method of claim 10 wherein, for erased bits, the adjusted state change verification voltage level imposes a threshold voltage lower than the last changed bit threshold voltage level.
13. The method of claim 12 wherein the adjusted state change verification voltage level is a predetermined amount, at least 100 millivolts, lower than the last changed bit threshold voltage level.
14. The method of claim 10 wherein, for programmed bits, the adjusted state change verification voltage level imposes a threshold voltage higher than the last changed bit threshold voltage level.
15. The method of claim 14 wherein the adjusted state change verification voltage level is a predetermined amount, at least 100 millivolts, higher than the last changed bit threshold voltage level.
16. A non-volatile memory (NVM) comprising:
a bitcell array comprising a plurality of bitcells for storing a plurality of bits;
a charge pump coupled to the plurality of bitcells; and
an NVM controller coupled to the bitcell array and to the charge pump, the NVM controller comprising control logic to control the charge pump to provide a normal bias voltage for altering the plurality of bits, to control the charge pump to provide at least one reduced bias voltage for altering the plurality of bits, wherein the at least one reduced bias voltage is less potent than the normal bias voltage, to determine a last changed bit threshold voltage level of a last changed bit of the plurality of bits, to control the charge pump to provide an adjusted state change verification voltage level, the adjusted state change verification voltage level selected from a group consisting of an erase verify voltage level, the erase verify voltage level being lower than a least erased bit threshold voltage level, and a program verify voltage level, the program verify voltage level being higher than a least programmed bit threshold voltage level, to perform a state change verification of the bits using the adjusted state change verification voltage level, to compare a number of failing bits which failed the state change verification to a failing bits threshold, and, when the number of failing bits is fewer than the failing bits threshold, to reject the NVM as defective.
17. The NVM of claim 16 wherein the control logic to control the charge pump to provide at least one reduced bias voltage for altering the plurality of bits further comprises:
control logic to control the charge pump to provide at least one reduced bias voltage for erasing the plurality of bits; and
the control logic to perform the state change verification of the bits using the adjusted state change verification voltage level further comprises:
control logic to perform an erase verify of the bits using the adjusted erase verification voltage level.
18. The NVM of claim 16 wherein the control logic to control the charge pump to provide at least one reduced bias voltage for altering the plurality of bits further comprises:
control logic to control the charge pump to provide at least one reduced bias voltage for programming the plurality of bits; and
the control logic to perform the state change verification of the bits using the adjusted state change verification voltage level further comprises:
control logic to perform a programming verification of the bits using the adjusted program verification voltage level.
19. The NVM of claim 16 wherein the NVM controller controls the charge pump to provide the adjusted state change verification voltage level, wherein the adjusted state change verification voltage level is a predetermined amount more stringent than the last changed bit threshold voltage level.
20. The NVM of claim 16 wherein the NVM controller implements a user margin read mode with fail bit count accessible via a user mode instruction.