High voltage diode
View Patent ↗A trench-isolated RESURF diode structure ( 100 ) is provided which includes a substrate ( 150 ) in which is formed anode ( 130, 132 ) and cathode ( 131 ) contact regions separated from one another by a shallow trench isolation region ( 114, 115 ), along with a non-uniform cathode region ( 104 ) and peripheral anode regions ( 106, 107 ) which define vertical and horizontal p-n junctions under the anode contact regions ( 130, 132 ), including a horizontal cathode/anode junction that is shielded by the heavily doped anode contact region ( 132 ).
1. A method of fabricating a semiconductor device, comprising in any order:
providing a semiconductor substrate region of a first conductivity type within an isolation structure comprising a deep trench isolation region formed to surround the semiconductor substrate region, a buried insulator layer formed at the bottom of the semiconductor substrate region, and at least a first shallow trench isolation region formed on a surface of the semiconductor substrate region;
forming a heavily doped first terminal contact region of the first conductivity type in a first terminal contact area of the semiconductor substrate region;
forming a heavily doped second terminal contact region of a second conductivity type in a second terminal contact area of the semiconductor substrate region to be spaced apart from the first terminal contact area;
forming a first terminal well region of the first conductivity type in the semiconductor substrate region under at least the first terminal contact area to be in ohmic contact with the first terminal contact region as finally formed; and
forming a second terminal well region of the second conductivity type in the semiconductor substrate region under at least the second terminal contact area to be in ohmic contact with the second terminal contact region as finally formed, where the second terminal well region extends laterally to a peripheral end portion that is located under the first terminal contact area of the semiconductor substrate region and that is adjacent to the first terminal well region as finally formed.
2. The method of claim 1 , where a cathode-anode junction formed between the first terminal well region and second terminal well region is shielded by the heavily doped first terminal contact region to enhance charging immunity.
3. The method of claim 1 , where the first terminal well region, the heavily doped first terminal contact region, and underlying semiconductor substrate region completely enclose the bottom and sides of the second terminal well region.
4. The method of claim 1 , where forming the second terminal well region comprises:
forming a deep terminal well region of the second conductivity type in the semiconductor substrate region around the heavily doped second terminal contact region; and
forming a shallow terminal well region of the second conductivity type in the semiconductor substrate region to extend laterally from the deep terminal well region to a peripheral end portion located under the first terminal contact area of the semiconductor substrate region.
5. The method of claim 4 , where forming the shallow terminal well region comprises implanting the shallow terminal well region so that the shallow terminal well region is separated from the heavily doped second terminal contact region by a lateral spacing dimension that is controlled to maximize breakdown voltage for the semiconductor diode device.
6. The method of claim 1 , where only a shallow trench isolation region separates the first and second terminal contact regions.
7. The method of claim 6 , where forming the first terminal well region comprises implanting the first terminal well region with an implant mask so that the first terminal well region is separated from the shallow trench isolation region by a lateral spacing dimension that is controlled to maximize breakdown voltage for the semiconductor diode device.
8. The method of claim 6 , where regions formed with material of the first conductivity type are formed as p-type regions, and where regions formed with material of the second conductivity type are formed as n-type regions.
9. A method for forming a high voltage diode device, comprising:
providing a semiconductor-on-insulator substrate comprising a semiconductor substrate layer formed over a buried insulator layer and surrounded by a deep trench isolation region;
forming shallow trench isolation regions on the substrate layer to define a first terminal contact opening separate from a second terminal contact opening by a first shallow trench isolation region; and then, in any order:
selectively implanting a heavily doped first terminal contact region of a first conductivity type in the substrate layer in the first terminal contact opening;
selectively implanting a deep first terminal well region of the first conductivity type in the substrate layer around the heavily doped first terminal contact region;
selectively implanting a shallow first terminal well region of the first conductivity type in the substrate layer to extend laterally to a peripheral end portion located under the second terminal contact opening; and
selectively implanting a peripheral second terminal well region of a second conductivity type in the substrate layer under the second terminal contact area to be positioned adjacent to the peripheral end portion of the shallow first terminal well region as finally formed; and then
selectively implanting a heavily doped second terminal contact region of the second conductivity type in the substrate layer in the second terminal contact opening so as to be spaced apart and separated from the heavily doped first terminal contact region by the first shallow trench isolation region.
10. The method of claim 9 , where the peripheral second terminal well region and heavily doped second terminal contact region form a RESURF layer in the substrate layer adjacent to the shallow first terminal well region.
11. The method of claim 9 , where selectively implanting the peripheral second terminal well region and heavily doped second terminal contact region comprises forming a cathode-anode junction in the substrate layer below the second terminal contact opening that is shielded by the heavily doped second terminal contact region to enhance charging immunity.