IP Library Granted Patent US 8,922,190
Granted Patent B2
US 8,922,190 · App. 13/714,415 · Granted Dec 30, 2014

Band gap reference voltage generator

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Quick Facts
Patent No.
US 8,922,190
App. No.
13/714,415
Granted
Dec 30, 2014
Kind
B2
Abstract

A band gap reference voltage generator has first and second current conduction paths between a first node and a second node. The first current conduction path has first resistive elements in series with a first forward-biased PN junction element. A tap is connected selectively to the first resistive elements through switches that are controllable to select a voltage divider ratio at the tap. The second current conduction path includes a second resistive element in series with a second PN junction element of greater current density than the first PN junction. A voltage error amplifier has inputs connected to the tap and the second PN junction element, and an output for providing a thermally compensated output voltage V REF . A feedback path applies the output voltage V REF through a third resistive element to the first node.

Claims (22)

1. A band gap reference voltage generator, comprising:

first and second forward-biased PN junction elements of different current densities;

a first current conduction path between a first node and a second node, including a plurality of first resistive elements that are connected in series between said first node and a third node, and said first PN junction element that is connected in series between said third node and said second node, wherein said first resistive elements are connected in a voltage divider configuration, wherein said plurality of first resistive elements includes a plurality of resistive trim elements having a ladder of 2n trim resistors of value R, a plurality of connector elements connecting said resistive trim elements in series, a first resistor having a resistance of R 1 -nR connected in series between the first node and the plurality of resistive trim elements, and a second resistor having a resistance of R 2 -nR connected in series between the third node and the plurality of resistive trim elements, wherein the n is a natural number;

a tap connected selectively to said first resistive elements through switch elements, wherein the switch elements are controllable to select a voltage divider ratio at said tap;

a second current conduction path between said first and second nodes, including a second resistive element connected in series between said first node and a fourth node, and said second PN junction element that is connected in series between said fourth node and said second node;

a voltage error amplifier having a first input connected to said tap, a second input connected to said fourth node, and an output for providing a thermally compensated output voltage; and

a feedback path for applying said output voltage to a series connection of a third resistive element with said first and second nodes.

2. The band gap reference voltage generator of claim 1 , wherein said PN junction elements comprise bipolar junction transistors (BJTs) having emitter, base and collector regions, said base regions being connected to said collector regions, and respective forward biased base-emitter junctions that are connected in series with said first and second current conduction paths.

3. The band gap reference voltage generator of claim 1 , wherein said switch elements are controllable to connect said tap selectively with a respective connector element and select a value of said voltage divider ratio at said tap that is settable bi-directionally about a central value.

4. The band gap reference voltage generator of claim 1 , further comprising a controller for controlling said switch elements to select and set said voltage divider ratio at said tap.

5. The band gap reference voltage generator of claim 4 , wherein said controller comprises a trim register and a decoder connected to the trim register.

6. The band gap reference voltage generator of claim 1 , wherein said first PN forward-biased junction element has a smaller current density than said second PN forward-biased junction element, and said plurality of first resistive elements presents a greater resistance than said second resistive element.

7. The band gap reference voltage generator of claim 1 , wherein said first input of said voltage error amplifier is an inverting input and said second input of said voltage error amplifier is a non-inverting input.

8. A method of making a band gap reference voltage generator having first and second forward-biased PN junction elements of different current densities, a first current conduction path between a first node and a second node, including a plurality of first resistive elements that are connected in series between said first node and a third node, and said first PN junction element that is connected in series between said third node and said second node, a second current conduction path between said first node and said second node, including a second resistive element connected in series between said first node and a fourth node, and said second PN junction element connected in series between said fourth node and said second node, the method comprising:

connecting said first resistive elements in a voltage divider configuration with a tap connected selectively to said first resistive elements through switch elements;

controlling said switch elements to select a voltage divider ratio at said tap;

providing a voltage error amplifier having a first input connected to said tap, a second input connected to said fourth node, and an output for providing a thermally compensated output voltage; and

providing a feedback path for applying said output voltage to a series connection of a third resistive element with said first and second nodes,

wherein said plurality of first resistive elements includes a plurality of resistive trim elements having a ladder of 2n trim resistors of value R, a plurality of connector elements connecting said resistive trim elements in series, a first resistor having a resistance of R 1 -nR connected in series between the first node and the plurality of resistive trim elements, and a second resistor having a resistance of R 2 -nR connected in series between the third node and the plurality of resistive trim elements, wherein the n is a natural number.

9. The method of claim 8 , wherein said PN junction elements comprise bipolar junction transistors (BJTs) having emitter, base and collector regions, said base regions being connected to said collector regions, and respective base-emitter junctions that are forward biased and connected in series with said first and second current conduction paths.

10. The method of claim 8 , wherein connecting said first resistive elements in a voltage divider configuration includes connecting said resistive trim elements in series with a plurality of connector elements, and connecting said switch elements between respective ones of said connector elements and said tap, and

controlling said switch elements includes connecting said tap selectively through one of said switch element with the respective connector element to select a value of said voltage divider ratio at said tap which is settable bidirectionally about a central value.

Assignments (21)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
MERGER Recorded Jan 3, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041144/0363 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
PATENT RELEASE Recorded Jan 14, 2016
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0671 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0685 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Apr 22, 2013
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Apr 22, 2013
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2012
From: WU, JIANZHOU; WANG, YANG
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 029467/0530 →