Split gate flash cell
View Patent ↗In one aspect, a disclosed method of fabricating a split gate memory device includes forming a gate dielectric layer overlying an channel region of a semiconductor substrate and forming an electrically conductive select gate overlying the gate dielectric layer. The method further includes forming a counter doping region in an upper region of the substrate. A proximal boundary of the counter doping region is laterally displaced from a proximal sidewall of the select gate. The method further includes forming a charge storage layer comprising a vertical portion adjacent to the proximal sidewall of the select gate and a lateral portion overlying the counter doping region and forming an electrically conductive control gate adjacent to the vertical portion of the charge storage layer and overlying the horizontal portion of the charge storage layer.
1. A method of fabricating a split gate memory device, the method comprising:
forming an electrically conductive select gate overlying a channel region of a semiconductor substrate;
forming a counter doping region in an upper region of the substrate outside of the channel region, wherein a proximal boundary of the counter doping region is laterally displaced from a proximal sidewall of the select gate, wherein a conductivity type of the channel region and a first conductivity type of the counter doping region are opposite and wherein an impurity concentration of the counter doping region exceeds an impurity concentration of the channel region;
forming an extension region aligned to a distal boundary of the select gate;
forming a heavily doped source/drain region adjacent to the extension region;
forming a charge storage layer comprising a vertical portion adjacent to the proximal sidewall of the select gate and a lateral portion overlying the counter doping region; and
forming an electrically conductive control gate adjacent to the vertical portion of the charge storage layer and overlying the horizontal portion of the charge storage layer;
wherein the extension region and the source/drain region have a conductivity type of the counter doping region and wherein an impurity concentration of the extension region is greater than an impurity concentration of the counter doping region and an impurity concentration of the source/drain region is greater than an impurity concentration of the extension region.
2. The method of claim 1 , wherein forming the charge storage layer includes:
thermally forming a first bottom oxide;
forming charge storage nanoclusters on the first bottom oxide; and
forming a second top oxide overlying the charge storage nanoclusters.
3. The method of claim 1 , wherein the channel region of the semiconductor substrate has a first conductivity type and wherein the counter doping region has a second conductivity type that is different than the first conductivity type.
4. The method of claim 1 , wherein forming the counter doping region includes:
forming a displacement structure on the proximal sidewall of the select gate; and
with the displacement structure in place, implanting a counter doping species into a counter doping region of the semiconductor substrate, wherein the counter doping region is laterally aligned to the displacement structure.
5. The method of claim 4 , wherein forming the displacement structure comprises thermally oxidizing the proximal sidewall of the select gate.
6. The method of claim 4 , wherein forming the displacement structure comprises:
depositing a dielectric layer conformally overlying the select gate; and
anisotropically etching the dielectric layer to remove portions of the dielectric layer overlying horizontal regions of the substrate.
7. The method of claim 4 , wherein:
a lateral displacement between the proximal boundary of the counter doping region and the proximal sidewall of the select gate is in the approximate range of 10 to 50 nm;
a depth of the counter doping region is in the approximate range of 20 to 80 nm; and
an impurity concentration of the counter doping region is in the approximate range of 10^16/cm 3 to 10^19 atoms/cm 3 .
8. A semiconductor fabrication process, comprising:
forming a gate dielectric overlying an upper surface of a semiconductor substrate;
forming an electrically conductive select gate overlying the gate dielectric and overlying a channel region of the semiconductor substrate wherein the channel region has a first conductivity type;
forming a displacement structure on a sidewall of the select gate;
forming a counter doping region of a second conductivity type in the semiconductor substrate laterally aligned to a sidewall of the displacement structure;
forming a charge storage layer including a plurality of nanoclusters;
forming a control gate electrode overlying the charge storage layer;
wherein forming the displacement structure includes:
depositing a conformal silicon dioxide layer over the select gate; and
etching the conformal silicon dioxide layer anisotropically to form spacer structures on sidewalls of the select gate.
9. The process of claim 8 , wherein depositing the conformal silicon dioxide layer comprises depositing a tetraethylorthosilicate (TEOS) layer.
10. The process of claim 8 , wherein forming the counter doping region includes implanting a counter doping species into the substrate.
11. The process of claim 8 , wherein forming the charge storage layer comprises:
removing the spacer structures; and
forming a charge storage dielectric overlying an upper surface of the substrate and adjacent a sidewall of the select gate.
12. The process of claim 11 , further comprising: forming nanocrystals in the charge storage dielectric.
13. A semiconductor storage device, comprising:
a gate dielectric layer overlying an upper surface of a well in a semiconductor substrate;
an electrically conductive select gate overlying the gate dielectric layer;
a counter doping region occupying an upper region of the substrate, wherein a proximal boundary of the counter doping region is laterally displaced with respect to a proximal sidewall of the select gate;
an extension region aligned to a distal boundary of the select gate;
a heavily doped source/drain region adjacent to the extension region;
a charge storage layer including a vertical portion adjacent to the proximal sidewall of the select gate and a lateral portion overlying the counter doping region; and
an electrically conductive control gate overlying the charge storage layer;
wherein the extension region and the source/drain region have a conductivity type of the counter doping region and wherein an impurity concentration of the extension region is greater than an impurity concentration of the counter doping region and an impurity concentration of the source/drain region is greater than an impurity concentration of the extension region.
14. The device of claim 13 , wherein a displacement between the select gate sidewall and the counter doping region exceeds approximately 10 nm.
15. The device of claim 13 , wherein the well comprises a 1st-type well and wherein the counter doping region is a second-type impurity distribution.
16. The device of claim 13 , wherein an impurity concentration of the counter doping region exceeds a doping concentration of the well.
17. The device of claim 13 , wherein a distal boundary of the counter doping region is aligned with a distal boundary of the control gate.
18. The device of claim 13 , wherein the charge storage layer includes a plurality of nanoclusters.