Non-volatile memory robust start-up using analog-to-digital converter
View Patent ↗In accordance with at least one embodiment, an onboard analog-to-digital converter (ADC) on a system-on-a-chip (SOC) is utilized to determine whether a charge pump output for a non-volatile memory (NVM) is correct or not. The SOC is directed to wait until the output is within an expected range before moving to the next step in a start-up procedure. If the maximum allowed start-up time is exceeded, an error signal is sent to the SOC such that the application can react to it.
1. A method comprising:
starting a charge pump for a non-volatile memory (NVM);
monitoring a voltage at an output of the charge pump with an analog-to-digital converter;
reading configuration information from the NVM in response to detecting with the analog-to-digital converter the voltage at the output to be within a predefined range;
configuring the NVM for operation based on the configuration information read from the NVM; and
enabling the NVM to be accessed in response to the configuring the NVM for operation.
2. The method of claim 1 wherein the monitoring the voltage at the output of the charge pump output further comprises:
allowing more time for the voltage at the output to be within the predefined range.
3. The method of claim 1 wherein the analog-to-digital converter is integrated on a common die as the charge pump to measure the voltage at the output.
4. The method of claim 1 wherein the monitoring the voltage at the output of the charge pump further comprises:
performing a restart of the charge pump.
5. The method of claim 1 wherein the monitoring the voltage at the output of the charge pump further comprises:
changing an operational parameter of the charge pump.
6. The method of claim 1 further comprising:
in response to detecting with the analog-to-digital converter the voltage at the output not to be within the predefined range, issuing an error status message.
7. The method of claim 6 wherein issuing the error status message further comprises:
issuing the error status message to a controller.
8. A method comprising:
starting a non-volatile memory (NVM) clock, wherein the NVM clock affects operation of an NVM charge pump;
starting the NVM charge pump;
verifying proper charge pump output voltage at an output of the NVM charge pump using an analog-to-digital converter (ADC);
reading configuration information from the NVM in response to the verifying the proper charge pump output voltage: and
proceeding with configuration of the NVM using configuration information read from the NVM after the proper charge pump output voltage has been verified.
9. The method of claim 8 wherein the proper charge pump output voltage is applied to a bit cell of a bit cell array of the NVM to perform a memory operation on the bit cell.
10. The method of claim 8 wherein the verifying proper charge pump output voltage using the ADC comprises:
iteratively measuring a charge pump output voltage of the NVM charge pump and comparing a measurement to a predefined range.
11. The method of claim 10 wherein the iteratively measuring the charge pump output voltage of the NVM charge pump and comparing the measurement to the predefined range comprises:
in response to the maximum start-up time having been exceeded, discontinuing the iteratively measuring the charge pump output voltage and instead issuing the error status message to a controller.
12. The method of claim 10 wherein the iteratively measuring the charge pump output voltage of the NVM charge pump and comparing the measurement to the predefined range further comprises:
iteratively adjusting an operational parameter of the charge pump.
13. The method of claim 8 further comprising:
allowing more time for the charge pump output voltage to achieve a value within the predefined range.
14. Apparatus comprising:
a non-volatile memory (NVM) bit cell array;
a charge pump, the charge pump coupled to the NVM bit cell array to provide, at an output, an output voltage to the array;
an analog-to-digital converter (ADC) module, the ADC module coupled to the output; and
a controller, the controller coupled to the ADC module, the controller comprising logic configured to cause the controller to initiate operation of the charge pump, to obtain a measurement of the output of the charge pump from the ADC module, to compare the measurement to an acceptable range, and, in response to the measurement being within the acceptable range, to read configuration information from the NVM bit cell array, to configure the apparatus for operation based on the configuration information read from the NVM bit cell array, and to allow access to the NVM bit cell array to proceed in response to configuration of the apparatus for operation.
15. The apparatus of claim 14 wherein the controller, in response to the measurement not being within the acceptable range, reiterates the obtaining the measurement of the output of the charge pump using the ADC module.
16. The apparatus of claim 15 wherein the controller, in response to the measurement not being within the acceptable range, allows the charge pump more time for the measurement of the output of the charge pump to come within the acceptable range.
17. The apparatus of claim 15 wherein the controller, in response to the measurement not being within the acceptable range, performs a restart of the charge pump.
18. The apparatus of claim 15 wherein the controller, in response to the measurement not being within the acceptable range, adjusts an operational parameter of the charge pump.
19. The apparatus of claim 18 wherein the operational parameter of the charge pump is selected from a group consisting of a clock frequency at which the charge pump operates and an output level of the charge pump.
20. The apparatus of claim 14 further comprising:
a clock having a clock output coupled to the charge pump, wherein the controller initiates operation of the clock, wherein the measurement of the output of the charge pump will not be within the acceptable range if a clock rate of the clock is not an acceptable clock rate.