Granted Patent B2

US 8,756,559 · App. 13/665,256 · Granted Jun 17, 2014

Abstract

Claims (57)

1. A method, comprising:

in a computer system, executing logic instructions for:

generating a circuit design;

simulating operation of the circuit design at a plurality of time slices;

determining type 1 damage and type 2 damage for each time slice;

providing a total type 1 damage as a sum of the type 1 damage for all of the slices in which type 1 damage is greater than type 2 damage;

providing a total type 2 damage as a sum of the type 2 damage for all of the slices in which type 2 damage is greater than type 1 damage;

determining a type 1 aging effect based on the total type 1 damage;

determining a type 2 aging effect based on the total type 2 damage;

adding the type 1 aging effect to the type 2 aging effect to obtain a total aging effect;

executing the simulation of the circuit design using the total aging effect to determine if the circuit design provides adequate lifetime performance,

wherein

the providing the total type 1 damage includes including one half of the type 1 damage in the total type 1 damage for each slice in which the type 1 damage equals the type 2 damage; and

the providing the total type 2 damage includes including one half of the type 2 damage in the total type 2 damage for each slice in which the type 2 damage equals the type 1 damage.

2. The method of claim 1 , wherein the executing the simulation comprises determining voltages at nodes of the circuit design at the plurality of time slices, wherein the circuit design includes a plurality of transistors wherein each transistor of the plurality of transistors is simulated at the plurality of time slices.

3. The method of claim 1 , wherein the determining the type 1 aging effect based on the total type 1 damage comprises an extrapolation of the type 1 damage for a predetermined time period.

4. The method of claim 3 , wherein the determining the type 1 aging effect is further characterized by the predetermined time period being an expected operational lifetime of the circuit design.

5. The method of claim 1 , the determining the type 2 aging effect based on the total type 2 damage comprises an extrapolation of the type 2 damage for a predetermined time period.

6. The method of claim 1 , further comprising providing an altered circuit design if the circuit design does not provide adequate lifetime performance.

7. The method of claim 1 , further comprising determining damage recovery for each time slice, and including the damage recovery in at least one of the total type 1 damage and the total type 2 damage.

8. The method of claim 1 , wherein the determining type 1 damage comprises determining bias temperature instability damage.

9. The method of claim 1 , wherein the determining type 2 damage comprises determining hot carrier injection damage.

10. A method, comprising:

in a computerized electronic design automation system:

generating a circuit design;

executing a simulation of the circuit design to provide voltages at nodes of a plurality of transistors that comprise the circuit design at a plurality of time slices;

determining damage due to a type 1 cause and a type 2 cause for each time slice of the plurality of time slices for each transistor of the plurality of transistors by determining which of the type 1 cause and the type 2 cause is a dominant cause of damage for each time slice;

adding the damage for all of the slices in which the type 1 cause is the dominant cause of damage to obtain a total type 1 damage for each transistor of the plurality of transistors;

determining an aging effect due to the type 1 cause based on the total type 1 damage for each transistor of the plurality of transistors;

adding the damage for all of the slices in which the type 2 cause is the dominant cause of damage to obtain a total type 2 damage;

determining an aging effect due to the type 2 cause based on the total type 2 damage for each transistor of the plurality of transistors;

adding the aging effect due to the type 1 cause to the aging effect due to the type 2 cause to obtain a total aging effect for each transistor of the plurality of transistors, wherein if the determining which of the type 1 cause and type 2 cause is a dominant cause of damage for each time slice results in a determination that the damage due to the type 1 cause is equal to the damage due to the type 2 cause, then attributing one half of the damage to each of the total type 1 damage and the total type 2 damage;

applying the total aging effect to the circuit design for each transistor of the plurality of transistors;

executing the simulation of the circuit design with the total aging effect added;

altering the circuit to obtain an altered circuit design if the testing the circuit design reveals inadequate performance.

11. The method of claim 10 , wherein the determining the aging effect due to the type 1 cause comprises extrapolating the total type 1 damage based on a predetermined time period to obtain a time-based type 1 damage estimate and using the time-based type 1 damage estimate to obtain the aging effect due to the type 1 cause.

12. The method of claim 11 , wherein the determining the aging effect due to the type 1 cause is further characterized by the predetermined time being an expected lifetime of an operation of the circuit design.

13. The method of claim 12 , further comprising making an integrated circuit having a circuit with the altered circuit design.

14. The method of claim 13 , wherein the executing the simulation is further characterized by the voltages at nodes comprising a gate/source voltage and a drain/source voltage for each transistor.

15. The method of claim 10 , wherein the determining damage is further characterized by the type 1 cause comprises bias temperature instability and the type 2 cause comprises hot carrier injection.

16. A method, comprising:

executing logic instructions in a computerized design system configured for:

generating a circuit design;

executing a simulation of the circuit design at a plurality of time slices to identify voltages at nodes of transistors that comprise the circuit design;

determining type 1 damage and type 2 damage for each time slice using the voltages at the nodes for each time slice of the plurality of time slices;

providing a total type 1 damage as a sum of the type 1 damage for all of the slices in which type 1 damage is greater than type 2 damage and including one half of the type 1 damage in the total type 1 damage for each slice in which the type 1 damage equals the type 2 damage;

providing a total type 2 damage as a sum of the type 2 damage for all of the slices in which type 2 damage is greater than type 1 damage and including one half of the type 2 damage in the total type 2 damage for each slice in which the type 2 damage equals the type 1 damage;

extrapolating the total type 1 damage for an expected lifetime of an operation of a circuit having the circuit design to obtain an extrapolated type 1 damage;

extrapolating the total type 2 damage for the expected lifetime of the operation of the circuit having the circuit design to obtain an extrapolated type 2 damage;

determining a type 1 aging effect based on the extrapolated type 1 damage;

determining a type 2 aging effect based on the extrapolated type 2 damage;

adding the type 1 aging effect to the type 2 aging effect to obtain a total aging effect;

executing the simulation of the circuit design using the total aging effect to determine if the circuit design provides adequate lifetime performance.

17. The method of claim 16 , further comprising:

altering the circuit design to obtain an altered circuit design if the testing the circuit design does not determine that the circuit design provides adequate performance; and

making an integrated circuit that includes a circuit according to the altered circuit design.

18. The method of claim 16 , wherein the determining the type 1 damage comprises determining bias temperature instability damage and determining the type 2 damage comprises determining hot carrier injection damage.

Assignments (20)