System and method for performing scan test
View Patent ↗A system for performing a scan test on an integrated circuit such as a System on a Chip (SoC) that may be packaged in different package types and with different features enabled includes a bypass-signal generator and a first scan-bypass circuit. The bypass-signal generator generates a first bypass signal based on chip package information. The first bypass signal indicates whether a first scan chain associated with a first non-common circuit block of the SoC is to be bypassed. The first scan chain is bypassed in response to the first bypass signal. By enabling partial scan testing based on package information, unintentional yield loss caused by a full scan test determining an SoC is faulty can be avoided.
1. A system for performing a scan test and memory built-in self test (BIST) on an integrated circuit (IC), the system comprising:
a bypass-signal generator that generates a first bypass signal based on a chip package information, the first bypass signal indicating whether a first scan chain associated with a first non-common functional circuit block of the IC is to be bypassed; and
a first scan-bypass circuit, connected to the bypass-signal generator and receiving the first bypass signal, for bypassing the first scan chain in response to the first bypass signal;
a first built-in self test (BIST) controller associated with a first non-common memory block of the IC; and
a first BIST-bypass circuit, connected to the bypass-signal generator and receiving the first bypass signal, for gating off an output of the first BIST controller in response to the first bypass signal.
2. The system of claim 1 , wherein the integrated circuit includes an input pin for receiving an enable signal that is provided to the bypass signal generator to initiate scan-bypass and BIST controller gating off testing.
3. The system of claim 1 , further comprising:
a first test clock gating circuit for gating a scan clock for the first scan chain in response to the first bypass signal.
4. The system of claim 3 , wherein the first test clock gating circuit further gates a BIST clock for the first BIST controller in response to the first bypass signal.
5. The system of claim 1 , wherein the first scan-bypass circuit includes a first multiplexer, and wherein the first bypass signal is provided to the first multiplexer as a selection signal.
6. The system of claim 1 , wherein the bypass-signal generator generates a second bypass signal based on the chip package information, and wherein the bypass-signal generator includes a lookup table for generating the first and second bypass signals.
7. The system of claim 6 , wherein the lookup table further comprises a logic decoding table for determining values of the first and second bypass signals based on the chip package information.
8. A system for performing a memory built-in self test (BIST) on an integrated circuit (IC), wherein the IC includes first and second non-common memory blocks, the system comprising:
first and second BIST controllers associated with the first and second non-common memory blocks;
a bypass-signal generator that generates a first and second bypass signals based on a chip package information, the first and second bypass signals indicating whether the first and second BIST controllers associated with the first and second non-common memory blocks of the IC are to be assigned with a don't-care condition regardless of whether one of the first and second non-common memory blocks has a problem; and
first and second BIST-bypass circuits, connected to the bypass-signal generator and receiving the first and second bypass signals, for gating the outputs of the first and second BIST controllers in response to the first and second bypass signals.
9. The system of claim 8 , further comprising:
a first test clock gating circuit for gating a BIST clock for one of the first and second BIST controllers in response to one of the first and second bypass signals.
10. The system of claim 8 , wherein the first BIST-bypass circuit includes a first pair of an OR gate and an AND gate coupled to an inverter, and wherein the first bypass signal is provided to the first pair of the OR gate and the AND gate to gate the output of the first BIST controller.
11. The system of claim 8 , wherein the bypass-signal generator includes a lookup table for generating the first and second bypass signals.
12. The system of claim 11 , wherein the lookup table further comprises a logic decoding table for determining values of the first and second bypass signals based on the chip package information.
13. A system for performing a scan test and memory built-in self test (BIST) on an integrated circuit (IC), the system comprising:
a bypass-signal generator that generates a first bypass signal based on a chip package information, the first bypass signal indicating whether a first scan chain associated with a first non-common functional circuit block of the IC is to be bypassed, and whether a first BIST controller associated with a first non-common memory block of the IC is to be assigned with a don't-care condition;
a first scan-bypass circuit, connected to the bypass-signal generator and receiving the first bypass signal, for bypassing the first scan chain in response to the first bypass signal; and
a first BIST-bypass circuit, connected to the bypass-signal generator and receiving the first bypass signal, for gating an output of the first BIST controller in response to the first bypass signal.
14. The system of claim 13 , further comprising:
a first test clock gating circuit, connected to the bypass-signal generator and receiving the first bypass signal, for gating a scan clock for the first scan chain and a BIST clock for the first BIST controller in response to the first bypass signal.
15. The system of claim 13 , wherein the first scan-bypass circuit includes a first multiplexer, and wherein the first bypass signal is provided to the first multiplexer as a selection signal.
16. A method for performing a memory built-in self test (BIST) on an integrated circuit (IC), the method comprising:
generating a first bypass signal based on a chip package information, the first bypass signal indicating whether a first BIST controller associated with a first non-common memory block of the IC is to be assigned with a don't care condition regardless of whether there is a problem in the first non-common memory block; and
gating an output of the first BIST controller in response to the first bypass signal.
17. The method of claim 16 , further comprising:
gating a BIST clock for the first BIST controller in response to the first bypass signal.