Methods of forming 3-D circuits with integrated passive devices
Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates coupled by through-substrate-vias (TSVs). An active device (AD) substrate has contacts on its upper portion. An isolator substrate is bonded to the AD substrate so that TSVs in the isolator substrate are coupled to the contacts on the AD substrate. An IPD substrate is bonded to the isolator substrate so that TSVs therein are coupled to an interconnect zone on the isolator substrate and/or TSVs therein. The IPDs of the IPD substrate are coupled by TSVs in the IPD and isolator substrates to devices in the AD substrate. The isolator substrate provides superior IPD to AD cross-talk attenuation while permitting each substrate to have small high aspect ratio TSVs, thus facilitating high circuit packing density and efficient manufacturing.
1. A method for forming a 3-D integrated circuit, comprising:
forming on separate substrates at least an active device chip, an isolator chip and an integrated passive device (IPD) chip, wherein the substrates of at least two of such chips have one or more conductor filled vias extending there through and wherein at least one of the one or more vias in the IPD chip is coupled to one or more integrated components on the substrate of the IPD chip;
stacking the active device chip, the isolator chip and the IPD chip so that a first via in a first of the at least two chips is aligned with a second via in another of the at least two chips, the first and second vias being two of the conductor filled vias; and
bonding the active device chip, the isolator chip, and the IPD chip together so that the first and second vias are electrically coupled.
2. The method of claim 1 , wherein the forming step comprises, forming the active device chip, the isolator chip and the IPD chip with one or more levels of interconnects on first surfaces thereof, wherein at least one of the interconnects in a first one of the chips is coupled during the bonding step with one or more of the conductor filled vias of a second one of the chips which is bonded to the first one of the chips in the bonding step.
3. The method of claim 1 , wherein the forming step comprises:
providing an initial substrate having a front face and a rear face;
etching a blind via cavity in the initial substrate extending from the front face toward the rear face;
filling the blind cavity with a conductor having an interior surface proximate a bottom of the cavity;
removing excess conductor from above the blind cavity to expose a first face of the conductor filling the blind cavity;
mounting the initial substrate on a support with the first face toward the support;
removing material from the rear face of the initial substrate thereby providing a thinned substrate having therein a conductor filled via of depth d extending there through and with the first face and the interior surface of the conductor in the cavity exposed; and
removing the support from the thinned substrate.
4. The method of claim 1 , wherein the substrate of the isolator chip has a resistivity of 1000 ohm-cm or greater.
5. The method of claim 1 , wherein the isolator chip has a thickness of 10 micrometers or larger.
6. The method of claim 1 , wherein the substrate of the IPD chip has a resistivity of 1000 ohm-cm or greater.
7. The method of claim 1 , wherein the substrate of the active device chip has a first thickness, the substrate of the isolator chip has a second thickness, and the substrate of the IPD chip has a third thickness, and at least one or both of the second and third thickness are at least 2-20 times the first thickness.
8. The method of claim 1 , wherein the isolator chip comprises a semiconductor material.
9. The method of claim 1 , wherein the IPD chip comprises a semiconductor material.
10. The method of claim 1 , wherein the first via is formed in the IPD chip, the second via is formed in the isolator chip and a third via is formed in the active device chip.
11. The method of claim 10 , wherein the third via is aligned with the first and second vias.
12. The method of claim 1 , the method comprising forming a further interconnect zone located between the substrate of the isolator chip and the substrate of the IPD chip, the further interconnect zone including a lateral conductor between two or more of the conductor filled vias.
13. The method of claim 12 , the method comprising forming a circuit element, wherein a first portion of the circuit element is formed in the IPD chip, and a second portion of the circuit element is formed in the further interconnect zone, and wherein the circuit element is selected from an RF transmission line with first and second conductive strips, and an inductor with an inductor loop and a patterned ground plane.
14. The method of claim 12 , wherein the further interconnect zone includes a ground plane.
15. The method of claim 12 , wherein the further interconnect zone includes an electrical shield.
16. The method of claim 12 , wherein the further interconnect zone includes an electromagnetic band gap structure having one or more tuned elements.
17. The method of claim 1 wherein in operation, the isolator chip is operable to improve RF isolation between at least one said integrated component of the IPD chip and at least one circuit element of the active device chip.
18. A method for forming a 3-D integrated circuit, comprising:
providing a first device chip, an isolator chip and a second device chip, each said chip comprising a respective substrate, wherein the substrates of at least two of such chips have one or more conductor filled vias extending there through and wherein at least some of the one or more conductor filled vias in the first or second device chip are coupled to one or more integrated components provided in the first or second device chip;
stacking the first device chip, the isolator chip, and the second device chip so that a first via in a first of the at least two chips is aligned with a second via in another of the at least two chips, the first and second vias being two of the conductor filled vias; and
bonding the first device chip, the isolator chip, and the second chip together so that the first and second vias are electrically coupled and so that the isolator chip provides physical separation between the first device chip and the second device chip.
19. The method of claim 18 , wherein at least one of the chips comprises a semiconductor material.
20. The method of claim 18 , wherein each of the chips comprises a semiconductor material.
21. A 3-D integrated circuit, comprising:
an active device chip comprising a substrate;
an integrated passive device (IPD) chip comprising a substrate; and
an isolator chip comprising a substrate and having a first side and second side, the first side bonded to the active device chip and the second side bonded to the IPD chip;
wherein the substrates of the IPD chip and the isolator chip have one or more conductor filled vias extending there through and electrically coupled, and
wherein at least one of the one or more vias in the IPD chip is coupled to one or more integrated components located on the opposite side of the substrate of the IPD chip from the isolator chip.
22. The 3-D integrated circuit of claim 21 wherein in operation, the isolator chip is operable to improve RF isolation between at least one said integrated component of the IPD chip and at least one circuit element of the active device chip.
23. A method for forming a 3-D integrated circuit, the method comprising:
providing an active device chip, an isolator chip and an integrated passive device (IPD) chip, each of these chips comprising a respective substrate, wherein the substrate of each of the isolator chip and the IPD chip has one or more conductive vias extending there through, the one or more conductive vias comprising a first via in the IPD chip and a second via in the isolator chip, the first via in the IPD chip being electrically coupled to one or more integrated components on the substrate of the IPD chip; and
stacking and bonding together the active device chip, the isolator chip and the IPD chip so that the isolator chip is between the active device chip and the IPD chip, and the first and second vias are electrically coupled.
24. The method of claim 23 wherein in operation, the isolator chip is operable to improve RF isolation between at least one said integrated component of the IPD chip and at least one circuit element of the active device chip.