Semiconductor chip, method of fabricating the same and stack package having the same
View Patent ↗A semiconductor chip may include a wafer, a semiconductor device formed on the wafer, a first dielectric layer formed on the wafer and the semiconductor device, a first metal interconnection formed on the first dielectric layer, a second dielectric layer formed on the first dielectric layer and the lower interconnection, and a third dielectric layer formed on the second dielectric layer. A second metal interconnection may be formed in the third dielectric layer, a first nitride layer formed on the third dielectric layer and the first metal interconnection, a via hole extending through the wafer, the first dielectric layer, the second dielectric layer, the third dielectric layer and the first nitride layer, a via formed in the via hole and a third metal interconnection formed on the first oxide layer, an exposed upper end of the via and the second metal interconnection.
1. A semiconductor chip comprising:
a wafer;
a semiconductor device formed on the wafer;
a first dielectric layer formed on the wafer and the semiconductor device;
a first metal interconnection formed on the first dielectric layer;
a second dielectric layer formed on the first dielectric layer and the first metal interconnection;
a third dielectric layer formed on the second dielectric layer;
a second metal interconnection formed in the third dielectric layer and having an exposed uppermost surface;
a first nitride layer formed on the third dielectric layer and the second metal interconnection, the first protective layer having a first hole exposing a portion of the second metal interconnection;
a via hole extending through the wafer, the first dielectric layer, the second dielectric layer, the third dielectric layer and the first nitride layer;
a via formed in the via hole, the via having an exposed lower end and an exposed upper end; and
a third metal interconnection formed on the exposed upper end of the via and the second metal interconnection exposed by the first hole and the second hole.
2. The semiconductor chip of claim 1 , wherein the semiconductor device comprises at least one of a DMOS transistor, a CMOS transistor, a bi-junction transistor and a diode.
3. The semiconductor chip of claim 1 , further comprising:
a plurality of lower vias extending through the first dielectric layer to electrically connect the semiconductor device to the first metal interconnection; and
a plurality of second vias extending through the second dielectric layer to electrically connect the first metal interconnection to the second metal interconnection.
4. The semiconductor chip of claim 1 , wherein the third metal interconnection layer is electrically connected to the via and the second metal interconnection.
5. The semiconductor chip of claim 4 , wherein the third metal interconnection layer comprises a multi-layered structure including a fourth metal interconnection layer and a fifth metal interconnection layer.
6. The semiconductor chip of claim 5 , wherein the interconnection layer includes a pad region.
7. The semiconductor chip of claim 1 , further comprising:
a first oxide layer formed on the first nitride layer and on sidewalls of the via hole, the first oxide layer including a second hole corresponding spatially to the first hole; and
a barrier metal layer formed interposed between the first oxide layer and the via.
8. The semiconductor chip of claim 7 , further comprising:
a second oxide layer formed on the first oxide layer and a portion of the third metal interconnection, the second oxide layer having a third hole exposing a portion of the third metal interconnection; and
a second nitride layer formed on the second oxide layer, the second nitride layer having a fourth hole corresponding spatially to the third hole.