Structures with through vias passing through a substrate comprising a planar insulating layer between semiconductor layers
View Patent ↗A through via contains a conductor ( 244, 262 ) passing through a substrate ( 140 ). The substrate can be SOI or some other substrate containing two semiconductor layers ( 140.1, 140.2 ) on opposite sides of an insulating layer ( 140 B). The through via includes two constituent vias ( 144.1, 144.2 ) formed from respective different sides of the substrate by processes stopping on the insulating layer ( 140 B). Due to the insulating layer acting as a stop layer, high control over the constituent vias' depths is achieved. Each constituent via is shorter than the through via, so via formation is facilitated. The conductor is formed by separate depositions of conductive material into the constituent vias from each side of the substrate. From each side, the conductor is deposited to a shallower depth than the through-via depth, so the deposition is facilitated. Other embodiments are also provided.
1. A manufacturing method comprising:
(1) obtaining a structure comprising:
a planar insulating layer having a first planar surface and a second planar surface opposite to the first planar surface;
a first semiconductor layer having a planar surface contacting the first planar surface of the planar insulating layer; and
a second semiconductor layer having a planar surface contacting the second planar surface of the planar insulating layer;
(2) removing part of the first semiconductor layer to form one or more first vias through the first semiconductor layer, the one or more first vias not passing through the planar insulating layer;
(3) removing part of the second semiconductor layer to form one or more second vias through the second semiconductor layer, the one or more second vias not passing through the planar insulating layer;
(4) forming one or more through-holes in the planar insulating layer to join each second via with a respective first via to form a respective through via passing through the first and second semiconductor layers and the planar insulating layer; and
(5) forming a conductor in each through via, the conductor providing a conductive path in the through via between the first and second semiconductor layers.
2. The method of claim 1 wherein in each of operations (2) and (3), the removing is selective to the planar insulating layer, the planar insulating layer providing a stop for the removing.
3. The method of claim 1 further comprising, before operation (5), forming an insulator over a sidewall of each of the first and second vias.
4. The method of claim 1 wherein:
each through via comprises the respective one first via and the respective one second via which are joined to form the through via;
the conductor in each through via comprises a first conductor portion present in the respective first via but not in the respective second via, and comprises a second conductor portion present in the respective second via but not in the respective first via;
operation (5) comprises:
(5A) forming each first conductor portion without entirely forming at least one second conductor portion;
(5B) before or after operation (5A), forming at least part of each second conductor portion.
5. The method of claim 4 wherein each second conductor portion is entirely formed in operation (5B), with no part of any second conductor portion being formed in operation (5A).
6. The method of claim 5 wherein the operation (5A) is performed before (4), and the operation (5B) is performed after (4).
7. The method of claim 5 wherein the operation (5A) is performed before (3).
8. The method of claim 4 wherein the method further comprises:
before operation (5A), forming an insulator over a sidewall of each first via;
before operation (5B), forming an insulator over a sidewall of each second via.
9. The method of claim 1 wherein the first and second semiconductor layers have the same thickness at each through via.
10. The structure of claim 1 wherein for each pair of a first via and a second via joined into a through via,
1/ k*Th 2 ≦Th 1≦ k*Th 2
wherein Th1 is the thickness of the first semiconductor layer at the through via, Th2 is the thickness of the second semiconductor layer at the through via, and k is a value greater than 1 but less than or equal to 10.
11. The method of claim 10 wherein k is less than or equal to 5.
12. The method of claim 10 wherein k is less than or equal to 3.