Patent Assignment
Reel/Frame 027853/0420
Assignment of Assignor's Interest
Recorded: 2012-03-13
Pages: 14
Assignor
ALLVIA, INC.
Executed: 2011-10-20
Assignee
INVENSAS CORPORATION
2702 ORCHARD PARKWAY, SAN JOSE, CALIFORNIA, 95134
Covered Properties
(49)
Plasma Processing Methods and Apparatus
Patent:
6,139,678 →
Application:
08/975,403 →
Article Holders and Holding Methods
Patent:
6,095,582 →
Application:
09/041,284 →
Integrated Circuits and Methods for Their Fabrication
Patent:
6,184,060 →
Application:
09/083,927 →
Plasma Processing Methods and Apparatus
Patent:
6,287,976 →
Application:
09/315,122 →
Packaging of Integrated Circuits and Vertical Integration
Patent:
6,322,903 →
Application:
09/456,225 →
Integrated Circuits and Methods for Their Fabrication
Plasma processing methods and apparatus
Patent:
6,323,134 →
Application:
09/519,281 →
Integrated Circuits and Methods for Their Fabrication
Patent:
6,420,209 →
Application:
09/538,869 →
Plasma Processing Methods and Apparatus
Patent:
6,627,039 →
Application:
09/542,519 →
Plasma processing methods and apparatus
Patent:
6,261,375 →
Application:
09/617,211 →
Detection and Handling of Semiconductor Wafer and Wafer-Like Objects
Patent:
6,631,935 →
Application:
09/632,236 →
Monitoring and Controlling Separate Plasma Jets to Achieve Desired Properties in a Combined Stream
Patent:
6,423,923 →
Application:
09/632,485 →
Packaging of Integrated Circuits and Vertical Integration
Patent:
6,693,361 →
Application:
09/716,092 →
Thinning and Dicing of Semiconductor Wafers Using Dry Etch, and Obtaining Semiconductor Chips with Rounded Bottom Edges and Corners
Birm and Gas Escape for Non-Contact Wafer Holder
Devices Having Substrates with Opening Passing Through the Substrates and Conductors in the Openings, and Methods of Manufacture
Semiconductor Structures Having Multiple Conductive Layers in an Opening, and Methods for Fabricating Same
Thinning and Dicing of Semiconductor Wafers Using Dry Etch, and Obtaining Semiconductor Chips with Rounded Bottom Edges and Corners
Article Holders and Article Positioning Methods
Monitoring and Controlling Separate Plasma Jets to Achieve Desired Properties in a Combined Stream
Monitoring and Controlling Separate Plasma Jets to Achieve Desired Properties in a Combined Stream
Fabrication of Semiconductor Structures Having Multiple Conductive Layers in an Opening
Integrated Circuit Structures with a Conductor Formed in a Through Hole in a Semiconductor Substrate and Protruding from a Surface of the Substrate
Methods of Manufacturing Devices Having Substrates with Opening Passing Through the Substrates and Conductors in the Openings
Detection and Handling of Semiconductor Wafers and Wafer-Like Objects
Clock Distribution Networks and Conductive Lines in Semiconductor Integrated
Integrated Circuits and Methods for Their Fabrication
Article Holders with Sensors Detecting a Type of Article Held by the Holder
Integrated Circuits and Methods for Their Fabrication
Method for Manufacturing a Structure Comprising a Substrate with a Cavity and a Semiconductor Integrated Circuit Bonded to a Contact Pad Located in the Cavity
Electroplating and Electroless Plating of Conductive Materials into Openings, and Structures Obtained Thereby
Wafering Method Comprising a Plasma Etch with a Gas Emitting Wafer Holder
Patent:
6,759,341 →
Application:
10/412,978 →
Plasma Processing Methods and Apparatus
Packaging Substrates for Integrated Circuits and Soldering Methods
Integrated Circuits and Packaging Substrates with Cavities, and Attachment Methods Including Insertion of Protruding Contact Pads into Cavities
Detection and Handling of Semiconductor Wafers and Wafer-Like Objects
Attachment of Integrated Circuit Structures and Other Substrates to Substrates with Vias
Semiconductor Structures Having Multiple Conductive Layers in an Opening, and Methods for Fabricating Same
Packaging Substrates for Integrated Circuits and Soldering Methods
Clock Distribution Networks and Conductive Lines in Semiconductor Integrated Circuits
Attachment of Integrated Circuit Structures and Other Substrates to Substrates with Vias
Integrated Circuits and Packaging Substrates with Cavities, and Attachment Methods Including Insertion of Protruding Contact Pads into Cavities
Dielectric Trenches, Nickel/Tantalum Oxide Structures,and Chemical Mechanical Polishing Techniques
Electroplating and Electroless Plating of Conductive Materials into Openings, and Structures Obtained Thereby
Agitation of Electrolytic Solution in Electrodeposition
Application:
11/744,046 →
Publication:
US 2008/0271995
Dielectric Trenches, Nickel/Tantalum Oxide Structures, and Chemical Mechanical Polishing Techniques
Dielectric Trenches, Nickel/Tantalum Oxide Structures, and Chemical Mechanical Polishing Techniques
Substrates with Through Vias with Conductive Features for Connection to Integrated Circuit Elements, and Methods for Forming Through Vias in Substrates
Structures with Through Vias Passing Through a Substrate Comprising a Planar Insulating Layer Between Semiconductor Layers
Related Assignments
(5)
Other recorded transfers of the patents in this record — the chain of ownership.
Change of Name
Mar 10, 2011
From: TRU-SI TECHNOLOGIES, INC.
To: ALLVIA, INC.
Reel/Frame 025932/0615 →
Change of Name
Mar 11, 2011
From: TRU-SI TECHNOLOGIES, INC.
To: ALLVIA, INC.
Reel/Frame 025939/0912 →
Security Interest
Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
Security Interest
Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
Release of Security Interest
Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION
Reel/Frame 052920/0001 →