IP Library Granted Patent US 6,882,030
Granted Patent B2
US 6,882,030 · App. 10/059,898 · Granted Apr 19, 2005

Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate

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Quick Facts
Patent No.
US 6,882,030
App. No.
10/059,898
Granted
Apr 19, 2005
Kind
B2
Abstract

To fabricate contacts on a wafer backside, openings ( 124 ) are formed in the face side of the wafer ( 104 ). A dielectric layer ( 140 ) and some contact material ( 150 ), e.g. metal, are deposited into the openings. Then the backside is etched until the contacts ( 150 C) are exposed and protrude out. The protruding portion of each contact has an outer sidewall ( 150 V). At least a portion of the sidewall is vertical or sloped outwards with respect to the opening when the contact is traced down. The contact is soldered to an another structure ( 410 ), e.g. a die or a PCB. The solder ( 420 ) reaches and at least partially covers the sidewall portion which is vertical or sloped outwards. The strength of the solder bond is improved as a result. The dielectric layer protrudes around each contact. The protruding portion ( 140 P) of the dielectric becomes gradually thinner around each contact in the downward direction. The thinned dielectric is more flexible, and is less likely detach from the contact when the contact is pulled sideways. Other embodiments are also described.

Claims (12)

1. A body comprising a semiconductor substrate which has a top surface and a bottom surface, wherein one or more through holes pass through the substrate between the top and bottom surfaces, the body comprising one or more circuit elements formed in and/or over the top surface of the semiconductor substrate;

a conductor formed in each through hole and protruding from the bottom surface of the semiconductor substrate, the conductor in each through hole being coupled to one or more of the circuit elements;

a dielectric separating the conductor in each through hole from the semiconductor substrate, wherein at each through hole the dielectric forms a protrusion on the bottom of the body around the conductor;

wherein at each through hole the conductor protrudes from the dielectric on the bottom of the body, the conductor thus having a protruding outer surface not covered by the dielectric, wherein at least a portion of the protruding outer surface is either vertical or sloped outwards, laterally away from the through hole, when the surface is traced down;

wherein throughout each protrusion formed by the dielectric, the dielectric becomes gradually thinner around the adjacent conductor as the protrusion is traced down.

2. An integrated circuit structure comprising:

a body comprising a semiconductor substrate which has a first surface and a second surface, wherein one or more through holes pass through the substrate between the first and second surfaces, the body comprising one or more circuit elements formed in and/or over the first surface of the semiconductor substrate;

a conductor formed in each through hole and protruding from a bottom surface of the semiconductor substrate, the conductor in each through hole being coupled to one or more of the circuit elements;

a dielectric separating the conductor in each through hole from the semiconductor substrate, wherein at each through hole the dielectric forms a protrusion on the bottom surface of the body around the conductor;

wherein throughout each protrusion formed by the dielectric, the dielectric becomes gradually thinner around the adjacent conductor as the protrusion is traced down.

3. The integrated circuit structure of claim 2 wherein at each through hole the conductor protrudes from the dielectric on the bottom surface of the body.

4. The integrated circuit structure of claim 2 in combination with a first substrate, wherein a protruding portion of each protruding conductor is attached to the first substrate.

Assignments (3)
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
CHANGE OF NAME Recorded Mar 10, 2011
From: TRU-SI TECHNOLOGIES, INC.
To: ALLVIA, INC.
Reel/Frame 025932/0615 →