Patent Assignment
Reel/Frame 025932/0615
Change of Name
Recorded: 2011-03-10
Pages: 4
Assignor
TRU-SI TECHNOLOGIES, INC.
Executed: 2007-11-16
Assignee
ALLVIA, INC.
657 N. PASTORIA AVENUE, SUNNYVALE, CALIFORNIA, 94085
Covered Properties
(21)
Plasma Processing Methods and Apparatus
Patent:
6,139,678 →
Application:
08/975,403 →
Article Holders and Holding Methods
Patent:
6,095,582 →
Application:
09/041,284 →
Integrated Circuits and Methods for Their Fabrication
Patent:
6,184,060 →
Application:
09/083,927 →
Plasma Processing Methods and Apparatus
Patent:
6,287,976 →
Application:
09/315,122 →
Packaging of Integrated Circuits and Vertical Integration
Patent:
6,322,903 →
Application:
09/456,225 →
Detection and Handling of Semiconductor Wafer and Wafer-Like Objects
Patent:
6,631,935 →
Application:
09/632,236 →
Monitoring and Controlling Separate Plasma Jets to Achieve Desired Properties in a Combined Stream
Patent:
6,423,923 →
Application:
09/632,485 →
Plasma Processing Comprising Three Rotational Motions of an Article Being Processed
Patent:
6,749,764 →
Application:
09/713,137 →
Devices Having Substrates with Opening Passing Through the Substrates and Conductors in the Openings, and Methods of Manufacture
Semiconductor Structures Having Multiple Conductive Layers in an Opening, and Methods for Fabricating Same
Thinning and Dicing of Semiconductor Wafers Using Dry Etch, and Obtaining Semiconductor Chips with Rounded Bottom Edges and Corners
Article Holders and Article Positioning Methods
Integrated Circuit Structures with a Conductor Formed in a Through Hole in a Semiconductor Substrate and Protruding from a Surface of the Substrate
Clock Distribution Networks and Conductive Lines in Semiconductor Integrated
Electroplating and Electroless Plating of Conductive Materials into Openings, and Structures Obtained Thereby
Wafering Method Comprising a Plasma Etch with a Gas Emitting Wafer Holder
Patent:
6,759,341 →
Application:
10/412,978 →
Packaging Substrates for Integrated Circuits and Soldering Methods
Integrated Circuits and Packaging Substrates with Cavities, and Attachment Methods Including Insertion of Protruding Contact Pads into Cavities
Attachment of Integrated Circuit Structures and Other Substrates to Substrates with Vias
Dielectric Trenches, Nickel/Tantalum Oxide Structures,and Chemical Mechanical Polishing Techniques
Agitation of Electrolytic Solution in Electrodeposition
Application:
11/744,046 →
Publication:
US 2008/0271995
Related Assignments
(3)
Other recorded transfers of the patents in this record — the chain of ownership.
Security Interest
Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
Security Interest
Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
Release of Security Interest
Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION
Reel/Frame 052920/0001 →