IP Library Granted Patent US 7,001,825
Granted Patent B2
US 7,001,825 · App. 11/014,464 · Granted Feb 21, 2006

Semiconductor structures having multiple conductive layers in an opening, and methods for fabricating same

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Quick Facts
Patent No.
US 7,001,825
App. No.
11/014,464
Granted
Feb 21, 2006
Kind
B2
Abstract

In some embodiments, a circuit structure comprises a semiconductor substrate, an opening passing through the substrate between a first side of the substrate and a second side of the substrate, and a plurality of conductive layers in the opening. In some embodiments, one conductive layer provides an electromagnetic shield that shields the substrate from AC signals carried by a contact pad made from another conductive layer on a backside of the substrate. The conductive layers can also be used to form capacitor/rectifier networks. Manufacturing methods also provided.

Claims (17)

1. A circuit manufacturing method comprising:

providing a structure in which an opening extends into a first side of a semiconductor substrate having a second side opposite the first side such that the opening penetrates partway through the substrate, a plurality of conductive layers overlay one another in the opening, and the conductive layers include a first conductive layer and a second conductive layer overlaying the first conductive layer such that the first and second conductive layers (i) are separated by insulating material in the opening, or (ii) form a P-N junction in the opening, or (iii) form a Schottky junction in the opening;

removing material along the second side of the substrate to reach the opening and expose the second conductive layer from the second side of the substrate;

wherein removing material along the second side of the substrate is performed such that the second conductive layer is largely flush with the second side of the substrate;

wherein:

the removal of the material is followed by etching the substrate along its second side; and

the second conductive layer protrudes from the opening along the second side of the substrate after the etch.

2. The method of claim 1 wherein removing material along the second side of the substrate is performed such that the first conductive layer is also largely flush with the second side of the substrate.

3. The method of claim 1 wherein the first and second conductive layers are separated by insulating material in the opening.

4. The method of claim 3 wherein removing material along the second side of the substrate is performed such that second conductive layer, the insulating material, and the first conductive layer are all largely flush with the second side of the substrate.

5. A circuit manufacturing method comprising:

providing a structure in which an opening extends into a first side of a semiconductor substrate having a second side opposite the first side such that the opening penetrates partway through the substrate, a plurality of conductive layers overlay one another in the opening, and the conductive layers include a first conductive layer and a second conductive layer overlaying the first conductive layer such that the first and second conductive layers (i) form a P-N junction in the opening, or (ii) form a Schottky junction in the opening;

removing material along the second side of the substrate to reach the opening and expose the second conductive layer from the second side of the substrate;

wherein removing material along the second side of the substrate is performed such that the second conductive layer is largely flush with the second side of the substrate.

6. The method of claim 5 wherein removing material along the second side of the substrate is performed such that the first conductive layer is also largely flush with the second side of the substrate.

7. The method of claim 5 wherein the first and second conductive layers form a P-N junction in the opening.

8. The method of claim 5 wherein the first and second conductive layers form a Schottky junction in the opening.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 13, 2012
From: ALLVIA, INC.
To: INVENSAS CORPORATION
Reel/Frame 027853/0420 →
CHANGE OF NAME Recorded Mar 11, 2011
From: TRU-SI TECHNOLOGIES, INC.
To: ALLVIA, INC.
Reel/Frame 025939/0912 →