Patent Assignment
Reel/Frame 025939/0912
Change of Name
Recorded: 2011-03-11
Pages: 4
Assignor
TRU-SI TECHNOLOGIES, INC.
Executed: 2007-11-16
Assignee
ALLVIA, INC.
657 N. PASTORIA AVENUE, SUNNYVALE, CALIFORNIA, 94085
Covered Properties
(25)
Integrated Circuits and Methods for Their Fabrication
Plasma processing methods and apparatus
Patent:
6,323,134 →
Application:
09/519,281 →
Integrated Circuits and Methods for Their Fabrication
Patent:
6,420,209 →
Application:
09/538,869 →
Plasma Processing Methods and Apparatus
Patent:
6,627,039 →
Application:
09/542,519 →
Plasma processing methods and apparatus
Patent:
6,261,375 →
Application:
09/617,211 →
Packaging of Integrated Circuits and Vertical Integration
Patent:
6,693,361 →
Application:
09/716,092 →
Thinning and Dicing of Semiconductor Wafers Using Dry Etch, and Obtaining Semiconductor Chips with Rounded Bottom Edges and Corners
Birm and Gas Escape for Non-Contact Wafer Holder
Monitoring and Controlling Separate Plasma Jets to Achieve Desired Properties in a Combined Stream
Monitoring and Controlling Separate Plasma Jets to Achieve Desired Properties in a Combined Stream
Fabrication of Semiconductor Structures Having Multiple Conductive Layers in an Opening
Methods of Manufacturing Devices Having Substrates with Opening Passing Through the Substrates and Conductors in the Openings
Detection and Handling of Semiconductor Wafers and Wafer-Like Objects
Integrated Circuits and Methods for Their Fabrication
Article Holders with Sensors Detecting a Type of Article Held by the Holder
Integrated Circuits and Methods for Their Fabrication
Method for Manufacturing a Structure Comprising a Substrate with a Cavity and a Semiconductor Integrated Circuit Bonded to a Contact Pad Located in the Cavity
Plasma Processing Methods and Apparatus
Detection and Handling of Semiconductor Wafers and Wafer-Like Objects
Semiconductor Structures Having Multiple Conductive Layers in an Opening, and Methods for Fabricating Same
Packaging Substrates for Integrated Circuits and Soldering Methods
Clock Distribution Networks and Conductive Lines in Semiconductor Integrated Circuits
Attachment of Integrated Circuit Structures and Other Substrates to Substrates with Vias
Integrated Circuits and Packaging Substrates with Cavities, and Attachment Methods Including Insertion of Protruding Contact Pads into Cavities
Electroplating and Electroless Plating of Conductive Materials into Openings, and Structures Obtained Thereby
Related Assignments
(4)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Mar 13, 2012
From: ALLVIA, INC.
To: INVENSAS CORPORATION
Reel/Frame 027853/0420 →
Security Interest
Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
Security Interest
Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
Release of Security Interest
Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION
Reel/Frame 052920/0001 →