Method of forming an interconnect structure
View Patent ↗A method of forming an interconnect structure in a semiconductor device in which via holes ( 62 ) defined in a dielectric layer are filled with a filler material ( 64 ), such as a porogen material, before a further dielectric layer ( 66 ) is deposited thereover. Trenches ( 72 ) are formed in the further dielectric layer and then the filler material exposed thereby in the via holes is removed. The method provides a robust process which affords improved via and trench profile control.
1. A method of forming an interconnect structure for a semiconductor device, comprising:
(a) depositing a first dielectric layer;
(b) patterning the first dielectric layer to form via holes in the first dielectric layer;
(c) filling the via holes with a filler material, wherein the filler material comprises an organic material that is selectively etchable with respect to the material of the first dielectric layer, and wherein the filler material has a decomposition temperature higher than 350° C.;
(d) depositing a second dielectric layer over the first dielectric layer which is selectively etchable with respect to the filler material, wherein said deposition of the second dielectric layer is carried out at a temperature below 350° C.;
(e) patterning the second dielectric layer to form trenches defining interconnections provided by the interconnect structure in the second dielectric layer;
(f) removing filler material exposed by the trenches from the via holes; and
(g) depositing electrically conductive material to fill the trenches and via holes.
2. A method of claim 1 wherein patterning step (e) includes depositing and patterning a photoresist layer formed of an organic material, and the patterned photoresist layer is etched away in the same etch process as the filler material in etch step (f).
3. A method of claim 1 wherein the filler material is removed in step (f) by decomposition thereof.
4. A method of claim 2 wherein the filler material is a porogen material.
5. A method of claim 1 wherein the via holes are filled with filler material in step (c) to define a substantially level upper surface without requiring a further planarization process.
6. A method of claim 1 wherein the first and second dielectric layers are formed of a low-k dielectric material having a dielectric constant below 3.
7. A method of claim 1 wherein the first dielectric layer is deposited in step (a) over an existing interconnect structure, and a self-aligned diffusion barrier layer is provided over electrically conductive material of the existing interconnect structure.
8. A method of claim 1 wherein the first dielectric layer is deposited in step (a) over an existing interconnect structure, and a diffusion barrier is provided over electrically conductive material of the existing interconnect structure, the method including a step after via hole formation step (b) and before filling step (c) of etching away areas of the diffusion barrier layer exposed by the via holes.
9. A method of claim 1 wherein the first dielectric layer is deposited in step (a) over an existing interconnect structure, and a diffusion barrier is provided over electrically conductive material of the existing interconnect structure, the method including a step after filler material etching step (f) of etching away areas of the diffusion barrier layer exposed by the via holes.