IP Library Granted Patent US 9,196,588
Granted Patent B2
US 9,196,588 · App. 13/668,840 · Granted Nov 24, 2015

EMI shield

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Quick Facts
Patent No.
US 9,196,588
App. No.
13/668,840
Granted
Nov 24, 2015
Kind
B2
Abstract

An EMI shield can be formed directly on a component, e.g., an unpackaged or packaged semiconductor die, by depositing and curing a curable composition which includes electrically conductive particles and a carrier. In examples, the shield can be configured as a grid or net of electrically conductive traces or lines. The curable electrically conductive material may be applied to the component surface in a flowable form and cured or allowed to cure to form the electrically conductive shield. The shield can be electrically coupled to contacts on an underlying circuit panel or support. The coupling material may be a conductive adhesive, and may be or may include a material the same as, or similar to, the shield material.

Claims (11)

1. A method of forming a shielded component, comprising: forming an electrically conductive shield including an open pattern of an electrically conductive material by depositing and curing a curable composition comprising electrically conductive particles and a carrier material on first portions of a surface of a component and on at least one sidewall extending away from the surface, such that at least second portions of the surface are free from the deposited composition, wherein the pattern of the electrically conductive material includes a plurality of first lines of the electrically conductive material extending in a first direction, and a plurality of second lines of the electrically conductive material extending in a second direction transverse to the first direction such that at least some of the second lines cross at least some of the first lines and the first and second lines surround open areas above at least some of the second portions.

2. The method of claim 1 , wherein the component is mounted to a circuit panel having an electrically conductive pad at a surface of the circuit panel, wherein the method further comprises depositing and curing a quantity of the curable composition onto at least the pad to electrically couple the shield with the conductive pad.

3. The method of claim 2 , wherein the component includes a first semiconductor die and a second semiconductor die stacked atop the first semiconductor die, wherein the second semiconductor die is disposed at or below the surface of the component, and each of the first and second semiconductor dies overlie the surface of the circuit panel.

4. The method of claim 1 , wherein the component is a packaged semiconductor die.

5. The method of claim 1 , wherein the component is a packaged semiconductor die having an encapsulation, and at least one of: the surface is a surface of the encapsulation, or the sidewalls are sidewalls of the encapsulation.

6. The method of claim 1 , wherein the component is an unpackaged semiconductor die, and the surface is a surface of the unpackaged die.

7. The method of claim 1 , the second direction is orthogonal to the first direction such that the at least some first lines and the at least some second lines form an orthogonal grid.

8. The method of claim 1 , wherein the second direction is other than orthogonal to the first direction such that the at least some second lines cross the at least some first lines at intersections which are non-orthogonal.

9. The method of claim 1 , wherein the first portions of the surface defines at least one continuous area and the second portions are fully enclosed within the at least one continuous area such that the open pattern has an appearance of a perforated sheet.

10. The method of claim 1 , wherein the shield further includes a solid pattern of the electrically conductive material deposited and cured with the open pattern.

11. The method of claim 10 , wherein a logo is unobstructed from view at the surface of the component notwithstanding the electrically conductive material.

Assignments (6)
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS LLC
To: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
Reel/Frame 073508/0745 →
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS CORPORATION
To: INVENSAS LLC
Reel/Frame 073941/0814 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2013
From: LEAL, JEFFREY S.
To: INVENSAS CORPORATION
Reel/Frame 029752/0198 →