Structures with through vias passing through a substrate comprising a planar insulating layer between semiconductor
View Patent ↗A through via contains a conductor ( 244, 262 ) passing through a substrate ( 140 ). The substrate can be SOI or some other substrate containing two semiconductor layers ( 140.1, 140.2 ) on opposite sides of an insulating layer ( 140 B). The through via includes two constituent vias ( 144.1, 144.2 ) formed from respective different sides of the substrate by processes stopping on the insulating layer ( 140 B). Due to the insulating layer acting as a stop layer, high control over the constituent vias' depths is achieved. Each constituent via is shorter than the through via, so via formation is facilitated. The conductor is formed by separate depositions of conductive material into the constituent vias from each side of the substrate. From each side, the conductor is deposited to a shallower depth than the through-via depth, so the deposition is facilitated. Other embodiments are also provided.
1. A manufacturing method comprising:
(1) obtaining a structure comprising:
a planar insulating layer having a first planar surface and a second planar surface opposite to the first planar surface;
a first semiconductor layer having a planar surface contacting the first planar surface of the planar insulating layer; and
a second semiconductor layer having a planar surface contacting the second planar surface of the planar insulating layer;
(2) forming one or more through vias each of which passes through the first and second semiconductor layers and the planar insulating layer; and
(3) forming a conductor in each through via, the conductor providing a conductive path in the through via between the first and second semiconductor layers;
wherein each through via comprises:
a respective first via portion passing through the first semiconductor layer and formed in operation (2) by removing part of the first semiconductor layer from a side opposite to the second semiconductor layer; and
a respective second via portion passing through the second semiconductor layer and formed in operation (2) by removing part of the second semiconductor layer from a side opposite to the first semiconductor layer;
wherein in each through via, the conductor comprises a first conductor portion present in the respective first via portion but not in the respective second via portion, and comprises a second conductor portion present in the respective second via portion but not in the respective first via portion;
wherein the method further comprises thinning the second semiconductor layer before forming any second via portion but after forming each first via portion and each first conductor portion.
2. The method of claim 1 wherein in operation (2), removing of the part of the first semiconductor layer and removing of the part of the second semiconductor layer are selective to the planar insulating layer, the planar insulating layer providing a stop for removing of the parts of the first and second semiconductor layers.
3. The method of claim 1 further comprising forming an insulator over a sidewall of each first via portion before forming a respective first conductor portion in the first via portion, and forming an insulator over a sidewall of each second via portion before forming a respective second conductor portion in the second via portion.
4. The method of claim 1 wherein the first and second semiconductor layers have the same thickness at each through via.
5. The method of claim 1 wherein for each through via,
1/ k*Th 2≦ Th 1≦ k*Th 2
wherein Th1 is the thickness of the first semiconductor layer at the through via, Th2 is the thickness of the second semiconductor layer at the through via, and k is a value greater than 1 but less than or equal to 10.
6. The method of claim 5 wherein k is less than or equal to 5.
7. The method of claim 5 wherein k is less than or equal to 3.
8. The method of claim 1 wherein the operation (2) wherein each through via comprises a respective third via portion passing through the planar insulating layer and formed by removing part of the planar insulating layer through the respective second via portion.
9. The method of claim 8 wherein each third via portion is formed after forming each first conductor portion.
10. The method of claim 1 wherein operation (1) comprises thinning the first semiconductor layer before operation (2).
11. The method of claim 1 further comprising attaching one or more integrated circuits to the first semiconductor layer on the side opposite to the second semiconductor layer, the one or more integrated circuits being electrically connected to at least one first conductor portion.
12. The method of claim 1 further comprising attaching one or more integrated circuits to the second semiconductor layer on the side opposite to the first semiconductor layer, the one or more integrated circuits being electrically connected to at least one second conductor portion.
13. The method of claim 1 further comprising forming at least two active circuit elements on respective opposite sides of the planar insulating layer, the active circuit elements being electrically interconnected through at least one conductor.
14. The method of claim 1 further comprising forming one or more transistor regions in at least one of the first and second semiconductor layers.