Semiconductor device and method for fabricating the same
View Patent ↗Embodiments relate to a semiconductor device and a method for fabricating the same. According to embodiments, a semiconductor device may include a first device, a silicon epitaxial layer formed on and/or over the first device, a second device formed on and/or over the silicon epitaxial layer, and a connection via formed through the silicon epitaxial layer, which may electrically interconnect the first device and the second device. According to embodiments, a method for fabricating a semiconductor device may include forming a first device, forming a silicon epitaxial layer on and/or over the first device, forming a connection via through the silicon epitaxial layer, and forming a second device on and/or over the silicon epitaxial layer such that the second device may be electrically connected to the connection via.
1. A device, comprising:
a first device including a plurality of first transistors formed on a substrate, a first multilayered interlayer insulation film formed over the substrate, a protective layer formed on the first multilayered interlayer insulation film, a plurality of first metal wires formed in the first multilayered interlayer insulation film, and a plurality of first contacts formed in the first multilayered interlayer insulation film to interconnect the plurality of first metal wires;
an etch stop layer formed on the protective layer;
a silicon epitaxial layer formed over the etch stop layer;
a second device formed over the silicon epitaxial layer, wherein the second device includes a plurality of second transistors on the silicon epitaxial layer, a second multilayered interlayer insulation film over the silicon epitaxial layer, a plurality of second metal wires formed in the second multilayered interlayer insulation film, and a plurality of second contacts formed in the second multilayered interlayer insulation film to interconnect the plurality of second metal wires; and
a connection via formed through the silicon epitaxial layer, the etch stop layer, and the protective layer to electrically interconnect the first device and the second device.
2. The device of claim 1 , wherein at least one of the plurality of second transistors in the second device is connected to at least one of the plurality of first metal wires of the first device through the connection via.
3. The device of claim 1 , wherein a source/drain region of at least one of the plurality of second transistors in the second device overlaps the connection via.
4. The device of claim 3 , wherein the connection via interconnects one of the plurality of first metal wires in the first device and the source/drain region of at least one of the plurality of second transistors in the second device through the etch stop layer, the silicon epitaxial layer, and the protective layer in the first device.
5. The device of claim 1 , wherein each of the first and second devices comprises at least one of a CPU, a SRAM, a DRAM, a flash memory, a logic device, a power IC, a control IC, an RF IC, and a sensor chip.
6. The device of claim 1 , wherein the etch stop layer comprises at least one of a SiN-based and a SiC-based material.
7. The device of claim 1 , wherein the silicon epitaxial layer has a thickness of approximately 2,000 to 20,000 Å.
8. The device of claim 1 , wherein the silicon epitaxial layer is in direct contact with the etch stop layer and the etch stop layer is in direct contact with the protective layer.