Infinitely stackable interconnect device and method
View Patent ↗A device having the capability for electrical, thermal, optical, and fluidic interconnections to various layers. Through-substrate vias in the interconnect device are filled to enable electrical and thermal connection or optionally hermetically sealed relative to other surfaces to enable fluidic or optical connection. Optionally, optical components may be placed within the via region in order to manipulate optical signals. Redistribution of electrical interconnection is accomplished on both top and bottom surfaces of the substrate of the interconnect chip.
1. A method for fabricating an infinitely stackable interconnect device, the method comprising:
forming a substrate from a single wafer having a first surface and an opposing second surface;
forming a recessed region in the substrate sized to accommodate at least one die in a stack;
forming at least one via in the substrate passing from the first surface to the opposing second surface;
at least partially filling the via with conductive material to form a conductive via;
forming at least one first interconnection pad on the first surface in electrical communication with the conductive via;
forming at least one second interconnection pad on the second surface in electrical communication with the conductive via;
forming at least one redistribution trace at one of said first and second surfaces of said substrate and in communication with at least one of said first and second interconnection pads;
mounting a die to the substrate in electrical communication with the first or second interconnection pad to form a packaged subsystem;
singulating the packaged subsystem by dicing and;
mounting the packaged subsystem to at least one subsequent packaged subsystem to form a stack.
2. The method of claim 1 , further comprising providing at least one via for thermal interconnection between the first surface and the second surface.
3. The method of claim 1 , wherein the substrate thickness is about 50-100 microns and the recessed region thickness is about 25-50 microns.
4. The method of claim 1 , further comprising the step of forming at least one redistribution trace at one of said surfaces of said substrate and in communication with at least one of said interconnection pads.
5. The method of claim 1 , further comprising forming a mechanical seal between the die and the substrate.
6. The method of claim 5 , wherein the mechanical seal is a sealing ring.
7. The method of claim 1 , wherein the substrate comprises a semiconductive material.
8. The method of claim 1 , wherein the substrate comprises an insulative material.
9. The method of claim 1 , further comprising providing a conductive plug positioned at the via.
10. An infinitely stackable interconnect device having interconnections for stacking the device with a subsequent device to form a stack, the device comprising:
a substrate having a first surface and an opposing second surface;
a recessed region in the substrate sized to accommodate at least one subsequent die in a stack;
at least one conductive via in the substrate passing from the first surface to the opposing second surface;
at least one first interconnection pad on said first surface in electrical communication with said conductive via;
at least one second interconnection pad on said opposing second surface in electrical communication with said conductive via;
at least one via for thermal interconnection between the first surface and the opposing second surface; and
means for electrical connection between at least one of said first interconnection pad and said second interconnection pad to at least one subsequent die;
wherein said subsequent die is mounted to said substrate in electrical communication with at least one of said first interconnection pad and said second interconnection pad.
11. The device of claim 10 , wherein the substrate thickness is about 50-100 microns and the recessed region thickness is about 25-50 microns.
12. The device of claim 10 , further comprising at least one redistribution trace at one of said surfaces of said substrate and in communication with at least one of said interconnection pads.
13. The device of claim 10 , wherein said conductive via has a sidewall taper in the range of about 84 degrees to 88 degrees.
14. The device of claim 10 , wherein said substrate comprises silicon.