Wafer level surface passivation of stackable integrated circuit chips
View Patent ↗An electrically insulative conformal coating is applied at least to the active (front) side and one or more sidewalls of the die during wafer processing. Also, a die has an electrically insulative conformal coating applied to at least the active (front) side and sidewalls. Also, assemblies include a stack of such die, electrically interconnected die-to-die; and assemblies include such a die or a stack of such die, electrically interconnected to underlying circuitry (for example in a substrate or a circuit board).
1. A method for making a passivated semiconductor die, comprising
providing a wafer having a front side in which semiconductor chip active regions are formed, the semiconductor chip active regions being bounded by saw streets, the semiconductor chip active regions having interconnect pads arranged in an interconnect margin along an interconnect edge thereof;
cutting the wafer to form die edges and die sidewalls (on at least some edges) prior to thinning the wafer to an eventual die thickness; and
applying a conformal coating to the front side of the wafer.
2. The method of claim 1 , further comprising
applying a die attach film to the back side of the wafer.
3. A method for making a passivated semiconductor die, comprising
providing a wafer having a front side in which semiconductor chip active regions are formed, the active regions being bounded by saw streets, the active regions having interconnect pads arranged in an interconnect margin along an interconnect edge thereof;
thinning the wafer to a die thickness;
cutting through the wafer on all streets to form die edges and a part of die sidewalls;
and applying a conformal coating the front side, the die edges, and the sidewalls.
4. A semiconductor wafer, having a front side in which semiconductor chip active regions are formed, the semiconductor chip active regions having interconnect pads arranged in an interconnect margin along an interconnect edge thereof, the semiconductor wafer further having trenches at the active side between active regions of chips, and having an electrically insulative conformal coating over at least the interconnect margins at the active surface and the trench surfaces.
5. The semiconductor wafer of claim 4 wherein the trenches that are fronted by interconnect margins of the die have a depth in the semiconductor wafer at least as great as a die thickness, and the trenches that are not fronted by interconnect margins of the die have a depth in the semiconductor wafer less than a die thickness.
6. A semiconductor die having a front side and a back side, and interconnect pads arranged in an interconnect margin in the front side along an interconnect edge thereof, and comprising an electrically insulative conformal coating over at least the interconnect margin and sidewalls adjacent thereto.
7. The semiconductor die of claim 6 , further comprising an electrically insulative film over the die backside.
8. An assembly comprising a stack of die as in claim 6 , electrically interconnected die-to-die.
9. An assembly comprising a stack of die as in claim 6 , electrically interconnected to underlying circuitry on a support.