IP Library Granted Patent US 8,349,736
Granted Patent B2
US 8,349,736 · App. 13/384,015 · Granted Jan 8, 2013

Semiconductor device manufacturing method and semiconductor device

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Quick Facts
Patent No.
US 8,349,736
App. No.
13/384,015
Granted
Jan 8, 2013
Kind
B2
Abstract

A base conductive member is formed on a surface and in a hole section of a substrate, and a resist is formed on a part of the base conductive member in which a conductive layer is not to be formed. The conductive layer is formed on a part except for the part in which the resist has been formed, and a mask metal is formed on the conductive layer. Then, the resist is removed, and the base conductive member is etched using the mask metal as a mask to form the conductive layer into a predetermined shape.

Claims (14)

1. A semiconductor device manufacturing method comprising:

forming a base conductive member on a surface of a substrate, and in a hole section formed in the substrate;

forming a resist on a part of the base conductive member;

removing the resist halfway through its thickness, after forming a conductive layer on a part except for a part at which the resist is formed and before forming the mask metal on the conductive layer;

forming a mask metal on the conductive layer with a surface of the conductive layer protected by the resist removed halfway;

removing the resist removed halfway after forming the mask metal; and

etching the base conductive member using the mask metal as a mask to form the conductive layer into a predetermined shape.

2. The semiconductor device manufacturing method according to claim 1 , comprising:

forming the conductive layer on a side wall and a bottom surface in the hole section formed in the substrate when forming the conductive layer on the part except for the part at which the resist is formed; and

forming the mask metal on the conductive layer formed on the side wall and the bottom surface in the hole section when forming the mask metal on the conductive layer.

3. The semiconductor device manufacturing method according to claim 1 , comprising:

forming a cap metal on an electrode pad section composed of the conductive layer when forming the mask metal.

4. The semiconductor device manufacturing method according to claim 1 , wherein

the mask metal is composed of a Ni base layer and an Au layer formed on the base layer.

Assignments (7)
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS CORPORATION
To: INVENSAS LLC
Reel/Frame 073941/0814 →
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS LLC
To: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
Reel/Frame 073508/0745 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 27, 2014
From: PANASONIC CORPORATION
To: INVENSAS CORPORATION
Reel/Frame 034042/0112 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 27, 2012
From: MURAGISHI, ISAO; KAI, TAKAYUKI; SAITO, DAISHIRO; YAMAMOTO, DAISUKE; KOIWASAKI, TAKESHI
To: PANASONIC CORPORATION
Reel/Frame 027930/0907 →