Technique for reducing parity bit-widths for check bit and syndrome generation for data blocks through the use of additional check bits to increase the number of minimum weighted codes in the hamming code H-matrix

1. An ECC technique for selecting parity bit-widths comprising:

establishing a minimum first number of check bits required for generation of check bits and syndromes for a desired Hamming distance based upon said first number of check bits;

utilizing a second number of check bits greater than said first number of check bits to increase the number of minimum weighted codes in a Hamming code H-matrix; and

generating said check bits and syndromes based upon said second number of check bits.

2. The technique of claim 1 further comprising:

utilizing said second number of check bits to reduce the width of a parity generation circuit.

3. An ECC technique for selecting parity bit-widths comprising:

establishing a minimum first number of check bits required for generation of check bits and syndromes for a desired Hamming distance based upon said first number of check bits;

adding at least one additional check bit to said first number of check bits to provide a second number of said check bits and increase a number of low weighted Hamming codes; and

reducing the width of a parity generating circuit in response to said second number of check bits.

4. The method of claim 3 wherein said number of low weighted Hamming codes comprises weight=2 codes.

5. The method of claim 4 wherein said technique is implemented in conjunction with an SEC/SED error correction process.

6. The method of claim 3 wherein said number of low weighted Hamming codes comprises weight=2 and 3 codes.

7. The method of claim 6 wherein said technique is implemented in conjunction with an SEC/DED error correction process.