IP Library Granted Patent US 8,344,503
Granted Patent B2
US 8,344,503 · App. 12/277,519 · Granted Jan 1, 2013

3-D circuits with integrated passive devices

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Quick Facts
Patent No.
US 8,344,503
App. No.
12/277,519
Granted
Jan 1, 2013
Kind
B2
Abstract

3-D ICs ( 18, 18′, 90 ) with integrated passive devices (IPDs) ( 38 ) having reduced cross-talk and high packing density are provided by stacking separately prefabricated substrates ( 20, 30, 34 ) coupled by through-substrate-vias (TSVs) ( 40 ). An active device (AD) substrate ( 20 ) has contacts on its upper portion ( 26 ). An isolator substrate ( 30 ) is bonded to the AD substrate ( 20 ) so that TSVs ( 4030 ) in the isolator substrate ( 30 ) are coupled to the contacts ( 26 ) on the AD substrate ( 20 ), and desirably has an interconnect zone ( 44 ) on its upper surface. An IPD substrate ( 34 ) is bonded to the isolator substrate ( 30 ) so that TSVs ( 4034 ) therein are coupled to the interconnect zone ( 44 ) on the isolator substrate ( 30 ) and/or TSVs ( 4030 ) therein. The IPDs ( 38 ) are formed on its upper surface and coupled by TSVs ( 4034, 4030 ) in the IPD ( 34 ) and isolator ( 30 ) substrates to devices ( 26 ) in the AD substrate ( 20 ). The isolator substrate ( 30 ) provides superior IPD ( 38 ) to AD ( 26 ) cross-talk attenuation while permitting each substrate ( 20, 30, 34 ) to have small high aspect ratio TSVs ( 40 ), facilitating high circuit packing density and efficient manufacturing.

Claims (25)

1. A 3-D integrated circuit (IC), comprising:

an active device (AD) substrate having an AD region thereon with device contacts therein;

an isolator substrate, separately formed from the AD substrate and having one or more through-substrate-vias (TSVs) therein adapted to be coupled to one or more of the device contacts in the AD region of the AD substrate;

an integrated passive device (IPD) substrate, separately formed from the AD substrate and the isolator substrate and having an IPD zone on its surface in which IPDs have been formed, and having a plurality of TSVs formed underlying the IPD zone through the IPD substrate, wherein the TSVs in the IPD substrate are coupled with the IPDs in the IPD zone, and at least some of the TSVs are adapted to couple one or more of the IPDs in the IPD zone to TSVs in the isolator substrate, and wherein at least some of the TSVs in the isolator substrate are vertically aligned with at least some of the TSVs in the IPD substrate; and

a further interconnect zone located between the isolator substrate and the IPD substrate, wherein the further interconnect zone includes a lateral conductor between two or more TSVs in a same substrate, thereby providing a connection selected from a group consisting of a cross-under connection between two or more IPDs in the IPD zone, and a cross-over connection between two or more device contacts of the AD substrate;

wherein at least one of the IPDs has a first element located in the IPD zone and a second element located in the further interconnect zone.

2. The integrated circuit of claim 1 , wherein at least some of the TSVs in the isolator substrate are coupled to some of the device contacts in the AD region on the AD substrate.

3. The integrated circuit of claim 1 , wherein some of the IPDs are coupled to other of the IPDs via the further interconnect zone.

4. The integrated circuit of claim 1 , wherein the isolator substrate has a resistivity of a 1000 ohm-cm or greater.

5. The integrated circuit of claim 1 , wherein the isolator substrate has a thickness in the range of about 10 and 200 micrometers or larger.

6. The integrated circuit of claim 1 , wherein the IPD substrate has a resistivity of a 1000 ohm-cm or greater.

7. The integrated circuit of claim 1 , wherein the AD substrate has a first thickness, the isolator substrate has a second thickness and the IPD substrate has a third thickness, and at least one or both of the second and third thickness are at least about 2-20 times the first thickness.

8. The integrated circuit of claim 1 , wherein the circuit element is an RF transmission line, the first portion of the circuit element is a first conductive strip of the RF transmission line, and the second portion of the circuit element is a second conductive strip of the RF transmission line.

9. The integrated circuit of claim 8 , wherein the first conductive strip and the second conductive strip form a differential signal pair.

10. The integrated circuit of claim 8 , wherein the second conductive strip is a ground.

11. The integrated circuit of claim 1 , wherein the circuit element is an inductor, the first portion of the circuit element is an inductor loop, and the second portion is a patterned ground plane.

12. A 3-D integrated circuit (IC), comprising:

an active device (AD) substrate having an AD region thereon with device contacts therein;

an isolator substrate, separately formed from the AD substrate and having one or more through-substrate-vias (TSVs) therein adapted to be coupled to one or more of the device contacts in the AD region of the AD substrate;

an integrated passive device (IPD) substrate, separately formed from the AD substrate and the isolator substrate and having an IPD zone on its surface in which IPDs have been formed, and having a plurality of TSVs formed underlying the IPD zone through the IPD substrate, wherein the TSVs in the IPD substrate are coupled with the IPDs in the IPD zone, and at least some of the TSVs are adapted to couple one or more of the IPDs in the IPD zone to TSVs in the isolator substrate; and

a further interconnect zone located between the isolator substrate and the IPD substrate, wherein the further interconnect zone includes a lateral conductor between two or more TSVs in the IPD substrate, thereby providing a cross-under connection between two or more IPDs in the IPD zone;

further comprising a circuit element, wherein a first portion of the circuit element is formed in the IPD zone, and a second portion of the circuit element is formed in the further interconnect zone.

13. The integrated circuit of claim 12 , wherein the further interconnect zone includes a ground plane.

14. The integrated circuit of claim 12 , wherein the further interconnect zone includes an electrical shield.

15. The integrated circuit of claim 12 , wherein the further interconnect zone includes an electromagnetic band gap structure having one or more tuned elements.

Assignments (33)
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS CORPORATION
To: INVENSAS LLC
Reel/Frame 073941/0814 →
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS LLC
To: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
Reel/Frame 073508/0745 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
RELEASE OF SECURITY INTEREST Recorded Jan 28, 2017
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: CITIBANK, N.A.
Reel/Frame 041114/0044 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
PATENT RELEASE Recorded Aug 17, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 039707/0471 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0807 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 12, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: INVENSAS CORPORATION
Reel/Frame 033093/0213 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2014
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUTOR, INC.
Reel/Frame 033134/0489 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2014
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 033134/0503 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded Mar 12, 2009
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 022380/0409 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 22, 2008
From: SANDERS, PAUL W.; JONES, ROBERT E.; PETRAS, MICHAEL F.; RAMIAH, CHANDRASEKARAM
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 022015/0904 →