Optimized charge sharing for data bus skew applications
View Patent ↗A circuit and method provide a charge sharing function during skewed data bus conditions in an integrated circuit memory. The charge sharing circuit includes two additional circuit blocks, one coupled to each of the capacitive lines in the charge-sharing line set, to provide the charge recycling feature. An extra clock signal is active one cycle early during a first clock period to trigger an extra drive circuit to generate a voltage differential on a first capacitive line that is similar to the voltage level generated when real data is being propagated. The presence of an extra voltage signal on the first capacitive line takes place earlier than what would normally happen and allows for proper charge sharing between a second capacitive line and the first capacitive line. Also, there is an additional control signal associated with a last clock period following normal non-skewed charge sharing. The additional control signal triggers a reference read circuit to generate data and a voltage on the first capacitive lines similar to the voltage present during real data for proper charge sharing. The additional read and drive circuit blocks are partial copies of the normal read and drive circuits so that a matching voltage can be generated on the appropriate capacitive signal lines.
1. A charge sharing circuit comprising:
a local read circuit;
a first amplifier circuit;
a capacitive local data line coupled between the local read circuit and the first amplifier circuit;
a drive circuit coupled to the first amplifier circuit;
a second amplifier circuit for providing an output signal;
a capacitive global data line coupled between the drive circuit and the second amplifier circuit;
a reference local read circuit coupled to the local data line; and
a reference drive circuit coupled to the global data line,
wherein the reference local read circuit comprises:
an inverter having an input for receiving a control signal and an output, and
a P-channel transistor having a gate coupled to the output of the inverter and a current path coupled between the local data line and a source of power supply voltage.
2. The charge sharing circuit of claim 1 wherein the local read circuit receives a first control signal and the reference local read circuit receives a second control signal.
3. The charge sharing circuit of claim 2 wherein the second control signal occurs after the first control signal.
4. The charge sharing circuit of claim 1 wherein the drive circuit receives a first control signal and the reference drive circuit receives a second control signal.
5. The charge sharing circuit of claim 4 wherein the second control signal occurs before the first control signal.
6. The charge sharing circuit of claim 1 wherein the reference local read circuit comprises means for supplying an additional signal to the local data line.
7. The charge sharing circuit of claim 6 wherein the additional signal comprises a positive-going signal.
8. The charge sharing circuit of claim 1 wherein the reference drive circuit comprises means for supplying an additional signal to the global data line.
9. The charge sharing circuit of claim 8 wherein the additional signal comprises a negative-going signal.
10. The charge sharing circuit of claim 1 further comprising a charge recycling circuit coupled between the capacitive local data line and the capacitive global data line.
11. A charge sharing circuit comprising:
a local read circuit;
a first amplifier circuit;
a capacitive local data line coupled between the local read circuit and the first amplifier circuit;
a drive circuit coupled to the first amplifier circuit;
a second amplifier circuit for providing an output signal;
a capacitive global data line coupled between drive circuit and the second amplifier circuit;
a reference local read circuit coupled to the local data line; and
a reference drive circuit coupled to the global data line,
wherein the reference drive circuit comprises:
an inverter having an input for receiving a control signal and an output; and
an N-channel transistor having a gate coupled to the output of the inverter and a current path coupled between the global data line and a source of reference voltage.
12. The charge sharing circuit of claim 11 wherein the local read circuit receives a first control signal and the reference local read circuit receives a second control signal.
13. The charge sharing circuit of claim 12 wherein the second control signal occurs after the first control signal.
14. The charge sharing circuit of claim 11 wherein the drive circuit receives a first control signal and the reference drive circuit receives a second control signal.
15. The charge sharing circuit of claim 14 wherein the second control signal occurs before the first control signal.
16. The charge sharing circuit of claim 11 wherein the reference local read circuit comprises means for supplying an additional signal to the local data line.
17. The charge sharing circuit of claim 16 wherein the additional signal comprises a positive-going signal.
18. The charge sharing circuit of claim 11 wherein the reference drive circuit comprises means for supplying an additional signal to the global data line.
19. The charge sharing circuit of claim 18 wherein the additional signal comprises a negative-going signal.
20. The charge sharing circuit of claim 11 further comprising a charge recycling circuit coupled between the capacitive local data line and the capacitive global data line.