Multiple bus charge sharing
View Patent ↗A charge-sharing circuit includes a first input bus pair, a second input bus pair, and an output bus pair. A capacitor is coupled between a first internal node and a second internal node. A first circuit selectively couples the first internal node to the first input bus pair, the second input bus pair and the output bus pair. A second circuit selectively couples the second internal node to the first input bus pair, the second input bus pair and the output bus pair. A third circuit selectively couples the first input bus pair to a reference voltage. A fourth circuit selectively couples the second input bus pair to the reference voltage. The third circuit is activated when the first input bus pair is inactive and charge is shared between the second bus pair and the output bus pair. The fourth circuit is activated when the second input bus pair is inactive and charge is shared between first bus pair and the output bus pair.
1. A charge-sharing circuit comprising:
a first input bus pair;
a second input bus pair;
an output bus pair;
a capacitor coupled between a first internal node and a second internal node;
a first circuit for selectively coupling the first internal node to the first input bus pair, the second input bus pair and the output bus pair;
a second circuit for selectively coupling the second internal node to the first input bus pair, the second input bus pair and the output bus pair;
a third circuit for selectively coupling the first input bus pair to a reference voltage; and
a fourth circuit for selectively coupling the second input bus pair to the reference voltage.
2. The charge-sharing circuit of claim 1 wherein the third circuit is activated when the first input bus pair is inactive and charge is shared between the second bus pair and the output bus pair.
3. The charge-sharing circuit of claim 1 wherein the fourth circuit is activated when the second input bus pair is inactive and charge is shared between first bus pair and the output bus pair.
4. The charge-sharing circuit of claim 1 wherein the first circuit comprises a pair of selectively activated P-channel transistors for coupling the first internal node to the first input bus pair.
5. The charge-sharing circuit of claim 1 wherein the first circuit comprises a pair of selectively activated P-channel transistors for coupling the first internal node to the second input bus pair.
6. The charge-sharing circuit of claim 1 wherein the first circuit comprises a pair of selectively activated N-channel transistors for coupling the first internal node to the output bus pair.
7. The charge-sharing circuit of claim 1 wherein the second circuit comprises a pair of selectively activated P-channel transistors for coupling the second internal node to the first input bus pair.
8. The charge-sharing circuit of claim 1 wherein the second circuit comprises a pair of selectively activated P-channel transistors for coupling the second internal node to the second input bus pair.
9. The charge-sharing circuit of claim 1 wherein the second circuit comprises a pair of selectively activated N-channel transistors for coupling the second internal node to the output bus pair.
10. The charge-sharing circuit of claim 1 wherein the third circuit comprises a pair of selectively activated P-channel transistors.
11. The charge-sharing circuit of claim 1 wherein the fourth circuit comprises a pair of selectively activated P-channel transistors.
12. The charge-sharing circuit of claim 1 wherein the capacitor comprises a plurality of capacitor-connected transistors.
13. The charge-sharing circuit of claim 12 wherein at least one of the capacitor-connected transistors comprises a switchable capacitor-connected transistor.
14. A charge-sharing circuit comprising:
a first amplifier circuit coupled to a first input bus;
a second amplifier circuit coupled to a second input bus;
a driver circuit coupled to the first amplifier circuit, the second amplifier circuit, and an output bus;
a first circuit for coupling the first input bus to a reference voltage during a first inactive mode; and
a second circuit for coupling the second input bus to the reference voltage during a second inactive mode.
15. The charge sharing circuit of claim 14 wherein the first amplifier circuit comprises a selectively enabled latch circuit.
16. The charge sharing circuit of claim 14 wherein the second amplifier circuit comprises a selectively enabled latch circuit.
17. The charge sharing circuit of claim 14 wherein the drive circuit comprises a capacitor coupled to first and internal nodes for sharing charge between the first input bus and the output bus or the second input bus and the output bus.
18. The charge sharing circuit of claim 14 wherein the first circuit comprises a pair of selectively enabled P-channel transistors.
19. The charge sharing circuit of claim 14 wherein the second circuit comprises a pair of selectively enabled P-channel transistors.
20. The charge sharing circuit of claim 14 wherein the reference voltage comprises a voltage of about VCC/2.
21. The charge-sharing circuit of claim 17 wherein the capacitor comprises a plurality of capacitor-connected transistors.
22. The charge-sharing circuit of claim 21 wherein at least one of the capacitor-connected transistors comprises a switchable capacitor-connected transistor.
23. A charge sharing method comprising:
sharing charge between a first bus and an output bus and holding a second bus to a constant voltage in a first operating mode; and
sharing charge between the second bus and the output bus and holding the first bus to a constant voltage in a second operating mode.
24. The charge sharing method of claim 23 wherein the second bus is inactive during the first operating mode.
25. The charge sharing method of claim 23 wherein the first bus is inactive during the second operating mode.