Patent Assignment
Reel/Frame 073508/0807
Change of Name
Recorded: 2025-11-24
Pages: 7
Assignor
INVENSAS LLC
Executed: 2022-08-15
Assignee
ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
3025 ORCHARD PARKWAY, SAN JOSE, CALIFORNIA, 95134
Covered Properties
(80)
Method of Forming Low Wire Loops and Wire Loops Formed Using the Method
Ball Grid Array Assignment
High Speed Interface Design
Two Layer Substrate Ball Grid Array Design
Wafer-Level Fabrication of Lidded Chips with Electrodeposited Dielectric Coating
Microelectronic Assembly with Multi-Layer Support Structure
Wafer Level Chip Packaging
Multiple Bus Charge Sharing
Wafer-Level Fabrication of Lidded Chips with Electrodeposited Dielectric Coating
Semiconductor Packaging Process Using Through Silicon Vias
Interconnection Element for Electric Circuits
Microelectronic Interconnect Element with Decreased Conductor Spacing
Structure and Method of Making Interconnect Element Having Metal Traces Embedded in Surface of Dielectric
Structure and Method of Making Interconnect Element, and Multilayer Wiring Board Including the Interconnect Element
Data Inversion Register Technique for Integrated Circuit Memory Testing
Patent:
44,726 →
Application:
13/313,792 →
Semiconductor Packaging Process Using Through Silicon Vias
Method of Making a Microelectronic Interconnect Element with Decreased Conductor Spacing
Microelectronic Assembly with Multi-Layer Support Structure
Rear-Face Illuminated Solid State Image Sensors
Microelectronic Interconnect Element with Decreased Conductor Spacing
Rear-Face Illuminated Solid State Image Sensors
Ball Bonding Metal Wire Bond Wires to Metal Pads
Methods and Structures to Repair Device Warpage
Microelectronic Package with Horizontal and Vertical Interconnections
Preferred State Encoding in Non-Volatile Memories
Wafer-Level Flipped Die Stacks with Leadframes or Metal Foil Interconnects
Patent:
9,490,195 →
Application:
14/883,864 →
Reversed Build-Up Substrate for 2.5D
Patent:
9,437,536 →
Application:
14/885,466 →
Multi-Chip Microelectronic Assembly with Built-Up Fine-Patterned Circuit Structure
Hybrid 3D/2.5D Interposer
Ssi Pop
Flipped Die Stacks With Multiple Rows Of Leadframe Interconnects
Patent:
9,508,691 →
Application:
14/971,384 →
Multi-Chip Package with Interconnects Extending Through Logic Chip
Patent:
9,553,071 →
Application:
14/992,178 →
Stiffened Wires for Offset Bva
Microelectronic Packages Having Stacked Die and Wire Bond Interconnects
New 2.5D Microelectronic Assembly and Method with Circuit Structure Formed on Carrier
Deformable Conductive Contacts
Enhanced Density Assembly Having Microelectronic Packages Mounted at Substantial Angle to Board
Patent:
9,728,524 →
Application:
15/198,615 →
Flipped Die Stack
Flipped Die Stack Assemblies with Leadframe Interconnects
Reversed Build-Up Substrate for 2.5D
Microelectronic Assembly with Redistribution Structure Formed on Carrier
Hd Color Imaging Using Monochromatic Cmos Image Sensors Integrated in 3D Package
Flipped Rf Filters and Components
Rear-face illuminated solid state image sensors
Anchoring Structure of Fine Pitch Bva
Microelectronic Package for Wafer-Level Chip Scale Packaging with Fan-Out
Bonding of Laminates with Electrical Interconnects
Enhanced Memory Reliability in Stacked Memory Devices
Patent:
9,778,984 →
Application:
15/340,883 →
Wafer-Level Flipped Die Stacks with Leadframes or Metal Foil Interconnects
Folding Thin Systems
'RDL-First' Packaged Microelectronic Device for a Package-on-Package Device
Packaged Microelectronic Device for a Package-on-Package Device
Flipped Die Stacks with Multiple Rows of Leadframe Interconnects
Microelectronic Interconnect Element with Decreased Conductor Spacing
Surface Integrated Waveguides and Circuit Structures Therefor
Wafer-Level Packaged Components and Methods Therefor
Dies-on-Package Devices and Methods Therefor
Package-On-Package Devices with Multiple Levels and Methods Therefor
Package-On-Package Devices with Same Level Wlp Components and Methods Therefor
Package-on-Package Devices with WLP Components with Dual RDLS for Surface Mount Dies and Methods Therefor
Package-On-Package Devices with Upper Rdl of Wlps and Methods Therefor
Multi-Chip Package with Interconnects Extending Through Logic Chip
Microelectronic Package with Horizontal and Vertical Interconnections
Tfd I/O Partition for High-Speed, High-Density Applications
Method and Apparatus for Stacking Devices in an Integrated Circuit Assembly
Multi-surface edge pads for vertical mount packages and methods of making package stacks
SSI PoP
Enhanced Memory Reliability in Stacked Memory Devices
Multi-Chip Package with Interconnects Extending Through Logic Chip
3D-Joining of Microelectronic Components with Conductively Self-Adjusting Anisotropic Matrix
Fan-Out Wafer Level Package with Resist Vias
Preferred State Encoding in Non-Volatile Memories
Formation of a Light-Emitting Diode Display
Enhanced Memory Reliability in Stacked Memory Devices
Methods of Forming Flipped Rf Filter Components
Method and Apparatus for Stacking Devices in an Integrated Circuit Assembly
Hybrid 3D/2.5D Interposer
Hd Color Imaging Using Monochromatic Cmos Image Sensors Integrated in 3D Package
Vertical Capacitors for Microelectronics
Bonding of Laminates with Electrical Interconnects
Related Assignments
(14)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Sep 10, 2013
From: HABA, BELGACEM; HUMPSTON, GILES; MARGALIT, MOTI
To: TESSERA, INC.
Reel/Frame 031266/0770 →
Assignment of Assignor's Interest
Sep 11, 2013
From: TESSERA, INC.
To: TESSERA TECHNOLOGIES IRELAND LIMITED
Reel/Frame 031264/0419 →
Change of Name
Sep 12, 2013
From: TESSERA TECHNOLOGIES IRELAND LIMITED
To: DIGITALOPTICS CORPORATION EUROPE LIMITED
Reel/Frame 031323/0555 →
Assignment of Assignor's Interest
Sep 26, 2013
From: ENDO, KIMITAKA; MASUDA, NORIHITO; SHIMADA, TOMOKAZU
To: SOCKETSTRATE, INC.
Reel/Frame 031350/0305 →
Change of Name
Sep 27, 2013
From: SOCKETSTRATE, INC.
To: TESSERA INTERCONNECT MATERIALS, INC.
Reel/Frame 031353/0975 →
Assignment of Assignor's Interest
Oct 7, 2013
From: PARRIS, MICHAEL C.; JONES, JR., OSCAR FREDERICK
To: UNITED MEMORIES, INC.; SONY CORPORATION
Reel/Frame 031422/0336 →
Assignment of Assignor's Interest
Oct 8, 2013
From: SONY CORPORATION
To: UNITED MEMORIES, INC.
Reel/Frame 031447/0746 →
Assignment of Assignor's Interest
Oct 11, 2013
From: UNITED MEMORIES, INC.
To: TESSERA INTELLECTUAL PROPERTIES, INC.
Reel/Frame 031464/0744 →
Change of Name
Oct 14, 2013
From: TESSERA INTELLECTUAL PROPERTIES, INC.
To: INVENSAS CORPORATION
Reel/Frame 031474/0817 →
Assignment of Assignor's Interest
Dec 4, 2013
From: RYU, CHANG MYUNG; ENDO, KIMITAKA; HABA, BELGACEM; KUBOTA, YOICHI
To: TESSERA, INC.
Reel/Frame 031712/0835 →
Security Interest
Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
Security Interest
Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
Release of Security Interest
Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION
Reel/Frame 052920/0001 →
Change of Name
Nov 24, 2025
From: INVENSAS CORPORATION
To: INVENSAS LLC
Reel/Frame 073508/0758 →