Wafer-level fabrication of lidded chips with electrodeposited dielectric coating
View Patent ↗A method is provided for fabricating a unit including a semiconductor element such as a sensor unit, e.g., for optical imaging. A semiconductor element has plurality of conductive features exposed at the front surface and semiconductive or conductive material exposed at at least one of the front and rear surfaces. At least some of the conductive features are insulated from the exposed semiconductive or conductive material. By electrodeposition, an insulative layer is formed to overlie the at least one of exposed semiconductive material or conductive material. Subsequently, a plurality of conductive contacts and a plurality of conductive traces are formed overlying the electrodeposited insulative layer, the conductive traces connecting the conductive features to the conductive contacts on the rear surface. The unit can be incorporated in a camera module having an optical element in registration with an imaging area of the semiconductor element.
1. A method of fabricating a microelectronic unit, the method comprising:
providing a semiconductor chip having a front surface, a rear surface remote from the front surface, at least one of conductive material or semiconductive material exposed at least at the front surface, and a plurality of first conductive contacts exposed at the front surface, at least some of the first conductive contacts being insulated from the at least one of exposed conductive material or semiconductive material;
electrophoretically depositing an insulative layer onto the at least one of exposed conductive material or semiconductive material;
forming a plurality of rear conductive traces on the rear surface of the semiconductor chip;
forming a plurality of front conductive traces on the insulative layer on the front surface of the semiconductor chip in conductive communication with the first conductive contacts;
electrophoretically depositing a further insulative layer onto at least a portion of the front conductive traces;
forming a plurality of further conductive traces on at least part of the further insulative layer on the front surface of the semiconductor chip in conductive communication with the front conductive traces; and
forming a plurality of edge conductive traces that extend between the front and the rear conductive traces, the edge conductive traces being formed atop edge surfaces that extend between the front surface and the rear surface of the semiconductor chip thereby conductively connecting one or more of the front conductive traces and the further conductive traces to the rear conductive traces.
2. The method of fabricating a microelectronic unit as recited in claim 1 , wherein the semiconductor chip and at least another semiconductor chip are attached together at one or more peripheral boundaries, the rear conductive traces are formed while the chips remain attached together, and the edge surfaces are defined by removing material of one or more of the semiconductor chip and the at least another semiconductor chip in alignment with the one or more peripheral boundaries.
3. The method of fabricating a microelectronic unit as recited in claim 1 , wherein the front surface of the semiconductor chip includes a conductive plane insulated from the first conductive contacts and the insulative material is electrophoretically deposited over the conductive plane.
4. The method of fabricating a microelectronic unit as recited in claim 3 , wherein the insulative layer is electrophoretically deposited over semiconductive material exposed at the rear surface of the semiconductor chip concurrent with the insulative layer being electrophoretically deposited over the conductive plane.
5. The method of fabricating a microelectronic unit as recited in claim 1 , wherein the insulative layer is electrophoretically deposited over semiconductive material exposed at the edge surfaces prior to the forming of the plurality of edge conductive traces.
6. The method of fabricating a microelectronic unit as recited in claim 2 , further comprising severing the semiconductor chip and the at least another semiconductor chip along one or more dicing lanes in alignment with the one or more peripheral boundaries.
7. The method of fabricating a microelectronic unit as recited in claim 1 , wherein the edge surfaces that extend between the front surface and the rear surface of the semiconductor chip are sloped at an acute angle with respect to the front surface of the semiconductor chip.
8. A method of fabricating a plurality of microelectronic units, the method comprising:
providing a plurality of semiconductor chips formed in a substrate, each one of the plurality of semiconductor chips being attached at one or more of its peripheral boundaries to at least another one of the plurality of semiconductor chips, and having a front surface, a rear surface remote from the front surface, at least one of conductive material or semiconductive material exposed at least at the front surface, and a plurality of first conductive contacts exposed at the front surface, at least some of the first conductive contacts being insulated from the at least one of exposed conductive material or semiconductive material;
electrophoretically depositing an insulative layer onto the at least one of exposed conductive material or semiconductive material of each one of the plurality of semiconductor chips; and
forming a respective plurality of rear conductive traces on the rear surface of each one of the plurality of semiconductor chips;
forming a respective plurality of front conductive traces on the insulative layer on the front surface of each one of the plurality of semiconductor chips;
electrophoretically depositing a further insulative layer onto at least a portion of the front conductive traces of each one of the plurality of semiconductor chips;
forming a respective plurality of further conductive traces on at least part of the further insulative layer at the front surface of each one of the plurality of semiconductor chips in conductive communication with the front conductive traces of that semiconductor chip; and
forming a respective plurality of edge conductive traces on each one of the plurality of semiconductor chips that extend between the respective front and rear conductive traces, the edge conductive traces being formed atop edge surfaces that extend between the front surface and the rear surface of each one of the plurality of semiconductor chips thereby conductively connecting one or more of the front conductive traces and the further conductive traces of that semiconductor chip to the rear conductive traces of that semiconductor chip.
9. The method of fabricating a plurality of microelectronic units as recited in claim 8 , wherein the respective rear conductive traces of each one of the plurality of semiconductor chips are formed while the plurality of semiconductor chips are attached together, and the edge surfaces of each one of the plurality of semiconductor chips are defined by removing semiconductor material in alignment with its one or more peripheral boundaries.
10. The method of fabricating a plurality of microelectronic units as recited in claim 9 , further comprising severing the plurality of semiconductor chips along one or more dicing lanes in alignment with the peripheral boundaries of each one of the plurality of semiconductor chips.
11. The method of fabricating a plurality of microelectronic units as recited in claim 8 , wherein the front surface of each one of the plurality of semiconductor chips includes a conductive plane insulated from the first conductive contacts, the insulative material of that semiconductor chip being electrophoretically deposited over the conductive plane.
12. The method of fabricating a plurality of microelectronic units as recited in claim 11 , wherein the insulative layer of each one of the plurality of semiconductor chips is electrophoretically deposited over semiconductive material exposed at the rear surface of that semiconductor chip concurrent with the insulative layer being electrophoretically deposited over the conductive plane.
13. The method of fabricating a plurality of microelectronic units as recited in claim 8 , wherein the insulative layer of each one of the plurality of semiconductor chips is electrophoretically deposited over semiconductive material exposed at the edge surfaces of that semiconductor chip prior to the forming of the plurality of edge conductive traces.
14. The method of fabricating a plurality of microelectronic units as recited in claim 8 , wherein the respective edge surfaces of each one of the plurality of semiconductor chips are sloped at an acute angle with respect to the front surface of that semiconductor chip.
15. A method of fabricating a plurality of microelectronic units, the method comprising:
providing a wafer that includes a plurality of semiconductor chips, each one of the plurality of chips being attached at one or more of its peripheral boundaries to at least another one of the plurality of semiconductor chips, and having a front surface, a rear surface remote from the front surface, at least one of conductive material or semiconductive material exposed at least at the front surface, and a plurality of first conductive contacts exposed at the front surface, at least some of the first conductive contacts being insulated from the at least one of exposed conductive material or semiconductive material;
electrophoretically depositing an insulative layer onto the at least one of exposed conductive material or semiconductive material of each chip of the wafer; and
forming a respective plurality of rear conductive traces on the rear surface of each chip of the wafer;
forming a respective plurality of front conductive traces on the insulative layer on the front surface of each chip of the wafer;
electrophoretically depositing a further insulative layer onto at least a portion of the front conductive traces of each one of the plurality of semiconductor chips;
forming a respective plurality of further conductive traces on at least part of the further insulative layer at the front surface of each one of the plurality of semiconductor chips in conductive communication with the front conductive traces of that semiconductor chip; and
forming a respective plurality of edge conductive traces on each one of the plurality of semiconductor chips that extend between the respective front and the rear conductive traces, the edge conductive traces being formed atop edge surfaces that extend between the front surface and the rear surface of each one of the plurality of semiconductor chips thereby conductively connecting one or more of the front conductive traces and the further conductive traces of that semiconductor chip to the rear conductive traces of that semiconductor chip.
16. The method of fabricating a plurality of microelectronic units as recited in claim 15 , wherein the rear conductive traces of each chip of the wafer are formed while the chips remain attached together, and the edge surfaces of each chip of the wafer are defined by removing material at the peripheral boundaries of each chip.
17. The method of fabricating a plurality of microelectronic units as recited in claim 15 , further comprising severing the chips of the wafer along one or more dicing lanes in alignment with the peripheral boundaries of each chip.
18. The method of fabricating a plurality of microelectronic units as recited in claim 15 , wherein the front surfaces of each chip of the wafer includes a respective conductive plane insulated from the first conductive contacts thereof, the insulative material of each chip being electrophoretically deposited over its conductive plane.
19. The method of fabricating a plurality of microelectronic units as recited in claim 18 , wherein the insulative layer of each chip of the wafer is electrophoretically deposited over semiconductive material exposed at the rear surface of each chip concurrent with the insulative layer being electrophoretically deposited over the conductive plane.
20. The method of fabricating a plurality of microelectronic units as recited in claim 15 , wherein the insulative layer of each chip of the wafer is electrophoretically deposited over semiconductive material exposed at the edge surfaces each chip prior to the forming of the plurality of edge conductive traces.
21. The method of fabricating a plurality of microelectronic units as recited in claim 15 , wherein the edge surfaces of each chip of the wafer are sloped at an acute angle with respect to the front surface of that chip.