Fan-out wafer level package with resist vias
Fan-out wafer level packages with resist vias are provided. In an implementation, an example wafer level process or panel fabrication process includes adhering a die to a carrier, applying a temporary resist layer over the die and the carrier, developing the resist layer to form channels or spaces, filling the channels or the spaces with a molding material, removing the remaining resist to create vias in the molding material, and metalizing the vias in the molding material to provide conductive vias for the microelectronics package. The methods automatically create good via and pad alignment. In another implementation, an example process includes adhering a die to a carrier, applying a permanent resist layer over the die and the carrier, developing the resist layer to form vias in the resist layer, and metalizing the vias in the remaining resist of the permanent resist layer to provide conductive vias for the microelectronics package. Assemblies may be constructed with the semiconductor dies face-up or face-down. One or more redistribution layers (RDLs) may be built on one or both sides of an assembly with resist vias.
1. A method, comprising:
adhering a die to a carrier for making a microelectronics package;
applying a resist layer as molding to the die and the carrier, the resist layer having a flat top surface:
developing parts of the resist layer with photolithography to form vias in the resist layer from the flat top surface of the resist layer to a conductive area of the die and to a conductive area of the carrier, wherein undeveloped parts of the resist layer remain permanently on the die and the carrier; and
conformally depositing a thin lining of a metal in the vias to provide conductive pathways through the resist layer to the conductive area of the die, and on the flat top surface of the resist layer, and to the conductive area of the carrier simultaneously thereby forming contact vias and vertical package-on-package (POP) vias in the resist layer in a single photolithography pass; and
etching the thin lining of the metal on the flat top surface of the resist layer to convert the thin lining of the metal to a patterned metal layer or a redistribution layer (RDL).
2. The method of claim 1 , wherein the resist layer comprises a photoimagable resist.
3. The method of claim 1 , further comprising drilling or forming one or more holes in the resist layer to form at least one of the vias.
4. The method of claim 1 , wherein depositing the thin lining of the metal in the vias further comprises lining the vias with the metal and filling a remaining space in the vias with a dielectric material or a nonconducting filler material.
5. The method of claim 1 , further comprising forming the patterned metal layer or the redistribution layer coupled to the conductive pathways.
6. The method of claim 1 , wherein the die is adhered face-up on the carrier.
7. The method of claim 1 , wherein the carrier comprises a layer of aluminum or a support material, and a layer of copper releasably attached to the aluminum or the support material.
8. The method of claim 1 , further comprising:
forming the contact vias and vertical package-on-package (POP) vias in the resist layer simultaneously in one lithography pass to provide an exact a substantially perfect registration of the contact vias and the vertical POP vias; and
the plating or depositing the thin lining of the metal in the contact vias and the vertical POP vias simultaneously and conformly in a single step, to make conductive contact vias and conductive vertical POP vias with exact registration.