Package-on-package devices with WLP components with dual RDLs for surface mount dies and methods therefor
Package-on-package (“PoP”) devices with WLP (“WLP”) components with dual RDLs (“RDLs”) for surface mount dies and methods therefor. In a PoP, a first IC die surface mount coupled to an upper surface of a package substrate. Conductive lines are coupled to the upper surface of the package substrate in a fan-out region. A molding layer is formed over the upper surface of the package substrate. A first and a second WLP microelectronic component are located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines. Each of the first and the second WLP microelectronic components have a second IC die located between a first RDL and a second RDL. A third and a fourth IC die are respectively surface mount coupled over the first and the second WLP microelectronic components.
1. A method for forming a package-on-package device, comprising:
obtaining a package substrate;
first surface mount coupling a first integrated circuit die to an upper surface of the package substrate;
coupling conductive lines to the upper surface of the package substrate in a fan-out region, the first conductive lines extending away from the upper surface of the package substrate;
forming a molding layer over the upper surface of the package substrate, around sidewall surfaces of the first integrated circuit die, and around bases and shafts of the conductive lines;
second surface mount coupling a first and a second wafer-level packaged microelectronic component located at a same level above an upper surface of the molding layer respectively to sets of upper portions of the conductive lines;
each of the first and the second wafer-level packaged microelectronic components having a second integrated circuit die located between a first redistribution layer and a second redistribution layer; and
third surface mount coupling a third and a fourth integrated circuit die respectively over the first and the second wafer-level packaged microelectronic components;
wherein each of the first and the second wafer-level packaged microelectronic components comprises:
the second integrated circuit die having first contacts in an inner third region of a first surface of the second integrated circuit die;
the first redistribution layer having second contacts in an inner third region of a first surface of the first redistribution layer and third contacts in an outer third region of a second surface of the first redistribution layer opposite the first surface thereof;
the second contacts of the first redistribution layer coupled for electrical conductivity to the first contacts of the second integrated circuit die with the first surface of the second integrated circuit die face-to-face with the first surface of the first redistribution layer; and
the third contacts offset from the second contacts for being positioned in a fan-out region for association at least with the outer third region of the second surface of the first redistribution layer, the third contacts being surface mount contacts.
2. The method according to claim 1 , wherein each of the first and the second wafer-level packaged microelectronic components comprises:
the second redistribution layer having fourth contacts in an inner third region of a first surface of the second redistribution layer and interconnects in an outer third region of a second surface of the second redistribution layer opposite the first surface thereof;
the second integrated circuit die having through die vias in an outer third region of the first surface and a second surface opposite the first surface;
the interconnects of the second redistribution layer coupled for electrical conductivity to the through die vias of the second integrated circuit die with the second surface of the second integrated circuit die face-to-face with the second surface of the second redistribution layer; and
the interconnects offset from the fourth contacts for being positioned in the fan-out region for association at least with the outer third region of the second surface of each of the first redistribution layer and the second redistribution layer.
3. The method according to claim 2 , wherein each of the third and the fourth integrated circuit dies comprises fifth contacts in an inner third region of respective surfaces of the third and the fourth integrated circuit dies.
4. The method according to claim 3 , wherein the third surface mount coupling comprises:
coupling the fourth contacts of the second redistribution layer for each of the first and the second wafer-level packaged microelectronic components for electrical conductivity respectively to the fifth contacts of the third and the fourth integrated circuit dies, respectively, with the respective surfaces of the third and the fourth integrated circuit dies face-to-face with the first surface of the second redistribution layer of the first and the second wafer-level packaged microelectronic components, respectively.
5. The method according to claim 1 , wherein the conductive lines are wire bond wires.
6. The method according to claim 1 , wherein the package substrate includes a fan-out wafer-level redistribution layer.
7. The method according to claim 1 , wherein:
the first integrated circuit die is a controller die;
each of the first and the second wafer-level packaged microelectronic component comprises a respective first memory die for the second integrated circuit die respectively thereof; and
the second and the third integrated circuit die are respective second memory dies.
8. The method according to claim 1 , wherein the conductive lines are conductive pillars.
9. The method according to claim 1 , wherein the conductive lines are conductive vias.