Semiconductor packaging process using through silicon vias

1. A microelectronic unit, comprising:

a semiconductor element having a front surface and a rear surface opposite the front surface, a microelectronic semiconductor device adjacent to the front surface, and contacts at the front surface, the semiconductor element having through holes extending from the rear surface through the semiconductor element and through the contacts, the contacts having outer surfaces facing away from the semiconductor element, and inner surfaces opposite from the outer surfaces, the through holes defining wall surfaces extending within the contacts from the inner surfaces towards the outer surfaces;

a monolithic dielectric layer lining portions of the through holes and overlying at least portions of the inner surfaces; and

a conductive element overlying the dielectric layer within the through holes, the conductive element contacting at least the wall surfaces within the contacts so as to conductively interconnect the contacts with unit contacts.

2. The microelectronic unit of claim 1 , wherein the semiconductor element further comprises contacts overlying the rear surface.

3. The microelectronic unit of claim 2 , wherein the holes are tapered, the holes becoming smaller with increasing distance from the rear surface.

4. The microelectronic unit of claim 3 , wherein walls of the holes are oriented at an angle of about 5 degrees or greater with respect to a normal to the rear surface.

5. The microelectronic unit of claim 4 , wherein the walls are oriented at an angle of less than or equal to about 40 degrees with respect to a normal to the rear surface.

6. The microelectronic unit of claim 1 , wherein an entire area of each hole is enclosed within an area of one of the contacts.

7. The microelectronic unit of claim 1 , further comprising a dielectric film overlying the inner surfaces of the contacts, wherein the monolithic dielectric layer overlies portions of the dielectric film.

8. A microelectronic unit, comprising:

a microelectronic element having a front surface and a rear surface opposite the front surface, and a plurality of contacts at the front surface;

the rear surface including at least one recess;

a plurality of through holes extending from the recess through the microelectronic element and through the contacts, the contacts having outer surfaces facing away from the semiconductor element and inner surfaces opposite from the outer surfaces, a dielectric layer lining at least portions of the through holes, the through holes defining wall surfaces extending within the contacts from the inner surfaces towards the outer surfaces; and

conductive vias within the through holes, the conductive vias contacting at least the wall surfaces within the contacts so as to interconnect the contacts with conductors within the at least one recess.

9. The microelectronic unit of claim 8 , wherein the conductors are interconnected with unit contacts exposed at locations of the rear surface beyond the at least one recess.

10. The microelectronic unit of claim 8 , wherein the conductive vias are separated from walls of the through holes by the dielectric layer.

11. The microelectronic unit of claim 8 , further comprising a microelectronic device adjacent to the front surface, the contacts being connected to the microelectronic device.

12. The microelectronic unit of claim 8 , wherein the at least one recess includes a plurality of blind holes, each blind hole being registered with at least one of the through holes.

13. The microelectronic unit of claim 12 , wherein the at least one recess includes a plurality of blind holes, each blind hole being registered with a single through hole.

14. The microelectronic unit of claim 12 , wherein each blind hole has a wall oriented at an angle of 5 degrees or greater with respect to a normal to the rear surface.

15. The microelectronic unit of claim 8 , wherein the at least one recess includes an elongated trench, the trench being registered with a plurality of the through holes.

16. The microelectronic unit of claim 15 , wherein each elongated trench has a wall oriented at an angle of 5 degrees or greater with respect to a normal to the rear surface.

17. The microelectronic unit of claim 8 , further comprising a dielectric layer lining a wall of the recess, the conductors being separated from the wall by the dielectric layer.

18. The microelectronic unit of claim 8 , further comprising a dielectric layer separating the contacts from the front surface of the semiconductor element, wherein the through holes extend through the dielectric layer and the conductive vias directly contact walls of the dielectric layer within the through holes.

19. The microelectronic unit of claim 8 , wherein the dielectric layer overlies at least portions of the inner surfaces of the contacts.

20. The microelectronic unit of claim 19 , further comprising a dielectric film overlying the inner surfaces of the contacts, wherein the dielectric layer overlies portions of the dielectric film.

21. A microelectronic unit, comprising:

a plurality of semiconductor elements stacked and joined together, each semiconductor element having a front surface defining a horizontal plane and a rear surface opposite the front surface, and having contacts at the front surface, the semiconductor elements being stacked in a vertical direction transverse to the horizontal plane;

a plurality of through holes extending through at least one of the stacked semiconductor elements and through contacts of the at least one semiconductor element, the contacts having outer surfaces facing away from the semiconductor element, and inner surfaces opposite from the outer surfaces, the through holes defining wall surfaces extending within the contacts from the inner surfaces towards the outer surfaces, the contacts of the plurality of stacked semiconductor elements being exposed within the through holes;

a monolithic dielectric layer lining portions of the through holes and overlying at least portions of the inner surfaces; and

a conductive layer overlying the dielectric layer within the through holes, the conductive layer contacting at least the wall surfaces within the contacts so as to in conductive communication with unit contacts of the microelectronic unit.

22. The microelectronic unit of claim 21 , wherein the unit contacts are exposed at an exterior of the microelectronic unit.

23. The microelectronic unit of claim 21 , wherein the through holes extend through contacts of a plurality of the stacked semiconductor elements.

24. The microelectronic unit of claim 21 , wherein the through holes do not extend entirely through all of the stacked semiconductor elements.

25. The microelectronic unit of claim 21 , wherein the front surface of at least one of the stacked semiconductor elements faces down and the unit contacts are exposed at an upwardly facing top face of the unit.

26. The microelectronic unit of claim 21 , wherein the front surface of at least one of the stacked semiconductor elements faces up and the unit contacts are exposed at an upwardly facing top face of the unit.

27. The microelectronic unit of claim 21 , further comprising a dielectric film overlying the inner surfaces of the contacts, wherein the monolithic dielectric layer overlies portions of the dielectric film.

28. A microelectronic unit, comprising:

a semiconductor element having a front surface, contacts at the front surface, a rear surface remote from the front surface, and edges extending between the front and rear surfaces;

a dielectric element extending outwardly from at least one of the edges of the semiconductor element, the dielectric element having a front surface and a rear surface remote from the front surface, the dielectric element bearing a plurality of conductive pads connected to the contacts, the dielectric element having a plurality of through holes extending between the front and rear surfaces and through the plurality of conductive pads;

a plurality of unit contacts exposed at an exterior of the microelectronic unit; and

conductive features extending from the contacts and within the through holes, the conductive features in conductive communication with the unit contacts.

29. The microelectronic unit of claim 28 , wherein the semiconductor element further comprises contacts overlying the rear surface.

30. The microelectronic unit of claim 29 , wherein the holes are tapered, the holes becoming smaller with increasing distance from the rear surface.

31. The microelectronic unit of claim 30 , wherein walls of the holes are oriented at an angle of about 5 degrees or greater with respect to a normal to the rear surface.

32. The microelectronic unit of claim 31 , wherein the walls are oriented at an angle of less than or equal to about 40 degrees with respect to a normal to the rear surface.