IP Library Granted Patent US 7,405,946
Granted Patent B2
US 7,405,946 · App. 11/122,370 · Granted Jul 29, 2008

Ball grid array assignment

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Quick Facts
Patent No.
US 7,405,946
App. No.
11/122,370
Granted
Jul 29, 2008
Kind
B2
Abstract

A pattern of contacts that includes high speed transmitter contacts disposed in a first portion of the pattern, where the high speed transmitter contacts are disposed in first ordered channels of adjacent transmitter differential pairs. High speed receiver contacts are disposed in a second portion of the pattern, where the first portion of the pattern is not interspersed with the second portion of the pattern, and the high speed receiver contacts are disposed in first ordered channels of adjacent receiver differential pairs. At least one unbroken line of other contacts is disposed between the first portion of the pattern and the second portion of the pattern, where the other contacts do not contain any high speed transmitter contacts and high speed receiver contacts. Low speed IO contacts are disposed in a third portion of the pattern. The first ordered channels are ordered to match an order of transmitter channels of a connector or another component on a printed circuit board to which the transmitter differential pairs are routed, and the second ordered channels are ordered to match an order of receiver channels of a connector or another component on a printed circuit board to which the receiver differential pairs are routed.

Claims (33)

1. A pattern of contacts comprising:

all high speed transmitter contacts disposed in a first portion of the pattern, where the high speed transmitter contacts are disposed in first ordered channels of adjacent transmitter differential pairs,

all high speed receiver contacts disposed in a second portion of the pattern, where the first portion of the pattern is not interspersed with the second portion of the pattern, and the high speed receiver contacts are disposed in second ordered channels of adjacent receiver differential pairs,

at least one unbroken line of other contacts disposed between the first portion of the pattern and the second portion of the pattern, where the other contacts do not contain any high speed transmitter contacts and high speed receiver contacts, and

all low speed IO contacts disposed in a third portion of the pattern,

where the first ordered channels are ordered to match an order of transmitter channels of at least one of a connector and another component on a printed circuit board to which the transmitter differential pairs are routed, and the second ordered channels are ordered to match an order of receiver channels of at least one of a connector and another component on a printed circuit board to which the receiver differential pairs are routed.

2. The pattern of claim 1 , wherein the other contacts comprise at least one of VSS contacts and VDD contacts.

3. The pattern of claim 1 , wherein the first ordered channels are ordered in a circular pattern.

4. The pattern of claim 1 , wherein the second ordered channels are ordered in a circular pattern.

5. The pattern of claim 1 , wherein the first portion of the pattern is disposed in a peripheral portion of the pattern, the second portion of the pattern is disposed in an interior portion of the pattern, and the unbroken line of other contacts separates the peripheral portion of the pattern from the interior portion of the pattern.

6. The pattern of claim 1 , wherein the first portion of the pattern is disposed in an interior portion of the pattern, the second portion of the pattern is disposed in a peripheral portion of the pattern, and the unbroken line of other contacts separates the peripheral portion of the pattern from the interior portion of the pattern.

7. A printed circuit board having a pattern of contacts comprising:

all high speed transmitter contacts disposed in a first portion of the pattern, where the high speed transmitter contacts are disposed in first ordered channels of adjacent transmitter differential pairs,

all high speed receiver contacts disposed in a second portion of the pattern, where the first portion of the pattern is not interspersed with the second portion of the pattern, and the high speed receiver contacts are disposed in second ordered channels of adjacent receiver differential pairs,

at least one unbroken line of other contacts disposed between the first portion of the pattern and the second portion of the pattern, where the other contacts do not contain any high speed transmitter contacts and high speed receiver contacts, and

all low speed IO contacts disposed in a third portion of the pattern,

where the first ordered channels are ordered to match an order of transmitter channels of at least one of a connector and another component on a printed circuit board to which the transmitter differential pairs are routed, and the second ordered channels are ordered to match an order of receiver channels of at least one of a connector and another component on a printed circuit board to which the receiver differential pairs are routed.

8. The printed circuit board of claim 7 , wherein the other contacts comprise at least one of VSS contacts and VDD contacts.

9. The printed circuit board of claim 7 , wherein the first ordered channels are ordered in a circular pattern.

10. The printed circuit board of claim 7 , wherein the second ordered channels are ordered in a circular pattern.

11. The printed circuit board of claim 7 , wherein the first portion of the pattern is disposed in a peripheral portion of the pattern, the second portion of the pattern is disposed in an interior portion of the pattern, and the unbroken line of other contacts separates the peripheral portion of the pattern from the interior portion of the pattern.

12. The printed circuit board of claim 7 , wherein the first portion of the pattern is disposed in an interior portion of the pattern, the second portion of the pattern is disposed in a peripheral portion of the pattern, and the unbroken line of other contacts separates the peripheral portion of the pattern from the interior portion of the pattern.

13. A package substrate having a pattern of contacts comprising:

all high speed transmitter contacts disposed in a first portion of the pattern, where the high speed transmitter contacts are disposed in first ordered channels of adjacent transmitter differential pairs,

all high speed receiver contacts disposed in a second portion of the pattern, where the first portion of the pattern is not interspersed with the second portion of the pattern, and the high speed receiver contacts are disposed in second ordered channels of adjacent receiver differential pairs,

at least one unbroken line of other contacts disposed between the first portion of the pattern and the second portion of the pattern, where the other contacts do not contain any high speed transmitter contacts and high speed receiver contacts, and

all low speed IO contacts disposed in a third portion of the pattern,

where the first ordered channels are ordered to match an order of transmitter channels of at least one of a connector and another component on a printed circuit board to which the transmitter differential pairs are routed, and the second ordered channels are ordered to match an order of receiver channels of at least one of a connector and another component on a printed circuit board to which the receiver differential pairs are routed.

14. The package substrate of claim 13 , wherein the other contacts comprise at least one of VSS contacts and VDD contacts.

15. The package substrate of claim 13 , wherein the first ordered channels are ordered in a circular pattern.

16. The package substrate of claim 13 , wherein the second ordered channels are ordered in a circular pattern.

17. The package substrate of claim 13 , wherein the first portion of the pattern is disposed in a peripheral portion of the pattern, the second portion of the pattern is disposed in an interior portion of the pattern, and the unbroken line of other contacts separates the peripheral portion of the pattern from the interior portion of the pattern.

18. The package substrate of claim 13 , wherein the first portion of the pattern is disposed in an interior portion of the pattern, the second portion of the pattern is disposed in a peripheral portion of the pattern, and the unbroken line of other contacts separates the peripheral portion of the pattern from the interior portion of the pattern.

Assignments (10)
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS LLC
To: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
Reel/Frame 073508/0807 →
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS CORPORATION
To: INVENSAS LLC
Reel/Frame 073508/0758 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
CHANGE OF NAME Recorded Jun 8, 2011
From: TESSERA INTELLECTUAL PROPERTIES, INC.
To: INVENSAS CORPORATION
Reel/Frame 026423/0286 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR'S NAME. DOCUMENT PREVIOUSLY RECORDED AT REEL 023778 FRAME 0084 Recorded Feb 12, 2010
From: LSI CORPORATION
To: TESSERA INTELLECTUAL PROPERTIES, INC.
Reel/Frame 023973/0941 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 13, 2010
From: LSI LOGIC CORPORATION
To: TESSERA INTELLECTUAL PROPERTIES, INC.
Reel/Frame 023778/0084 →
CHANGE OF NAME Recorded Nov 19, 2009
From: LSI LOGIC CORPORATION
To: LSI CORPORATION
Reel/Frame 023546/0137 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 5, 2005
From: HALL, JEFFREY A.; GHAHGHAHI, FARSHAD
To: LSI LOGIC CORPORATION
Reel/Frame 016538/0386 →