IP Library Granted Patent US 7,327,043
Granted Patent B2
US 7,327,043 · App. 11/205,364 · Granted Feb 5, 2008

Two layer substrate ball grid array design

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Quick Facts
Patent No.
US 7,327,043
App. No.
11/205,364
Granted
Feb 5, 2008
Kind
B2
Abstract

A routing pattern for high speed signals for a package substrate. Electrically conductive bond fingers are disposed on a first surface of the package substrate. The first surface is adapted to receive an integrated circuit in an attachment zone, and the bond fingers are disposed in at least two substantially concentric rings around the attachment zone. The bond fingers of the innermost ring of bond fingers are all routed to electrically conductive first traces disposed on a first layer of the package substrate. The bond fingers other that those on the innermost ring of bond fingers are all routed to electrically conductive second traces disposed on a separate second layer of the package substrate. The package substrate has electrically conductive traces on only the first layer and the second layer. Electrically conductive contacts are disposed on a substantially opposing second surface. The first traces are all routed to a first set of the contacts that are all disposed within an innermost portion of the second surface, and the second traces are all routed to a second set of the contacts that are all disposed within an outermost portion of the second surface.

Claims (40)

1. A routing pattern for high speed signals for a package substrate, the routing pattern comprising:

electrically conductive bond fingers on a first surface of the package substrate, where the first surface is adapted to receive an integrated circuit in an attachment zone, the bond fingers disposed in at least two substantially concentric rings around the attachment zone,

the bond fingers of an innermost ring of bond fingers all routed to electrically conductive first traces disposed on a first layer of the package substrate,

the bond fingers other than those on the innermost ring of bond fingers all routed to electrically conductive second traces disposed on a second layer of the package substrate that is a separate layer from the first layer of the package substrate,

the package substrate having electrically conductive traces on only the first layer and the second layer, and

electrically conductive contacts disposed on a second surface of the package substrate that substantially opposes the first surface, the first traces all routed to a first set of the contacts that are all disposed within an innermost portion of the second surface, and the second traces all routed to a second set of the contacts that are all disposed within an outermost portion of the second surface.

2. The routing pattern of claim 1 , wherein none of the first traces are separated by non signal carrying traces.

3. The routing pattern of claim 1 , wherein none of the second traces are separated by non signal carrying traces.

4. The routing pattern of claim 1 , wherein a third set of contacts for power and ground only is disposed interior to the first set of contacts on the second surface.

5. The routing pattern of claim 1 , wherein the first set of contacts is disposed in a substantially concentric ring on the second surface.

6. The routing pattern of claim 1 , wherein the second set of contacts is disposed in at least one substantially concentric ring at a peripheral edge of the second surface.

7. A routing pattern for high speed signals for a package substrate, the routing pattern comprising:

electrically conductive bond fingers on a first surface of the package substrate, where the first surface is adapted to receive an integrated circuit in an attachment zone, the bond fingers disposed in at least two substantially concentric rings around the attachment zone,

the bond fingers of an innermost ring of bond fingers all routed to electrically conductive first traces disposed on a first layer of the package substrate, wherein none of the first traces are separated by non signal carrying traces,

the bond fingers other than those on the innermost ring of bond fingers all routed to electrically conductive second traces disposed on a second layer of the package substrate that is a separate layer from the first layer of the package substrate, wherein none of the second traces are separated by non signal carrying traces,

the package substrate having electrically conductive traces on only the first layer and the second layer, and

electrically conductive contacts disposed on a second surface of the package substrate that substantially opposes the first surface, the first traces all routed to a first set of the contacts that are all disposed within an innermost portion of the second surface, and the second traces all routed to a second set of the contacts that are all disposed within an outermost portion of the second surface.

8. The routing pattern of claim 7 , wherein a third set of contacts for power and ground only is disposed interior to the first set of contacts on the second surface.

9. The routing pattern of claim 7 , wherein the first set of contacts is disposed in a substantially concentric ring on the second surface.

10. The routing pattern of claim 7 , wherein the second set of contacts is disposed in at least one substantially concentric ring at a peripheral edge of the second surface.

11. A routing pattern for high speed signals for a package substrate, the routing pattern comprising:

electrically conductive bond fingers on a first surface of the package substrate, where the first surface is adapted to receive an integrated circuit in an attachment zone, the bond fingers disposed in at least two substantially concentric rings around the attachment zone,

the bond fingers of an innermost ring of bond fingers all routed to electrically conductive first traces disposed on a first layer of the package substrate, wherein none of the first traces are separated by non signal carrying traces,

the bond fingers other than those on the innermost ring of bond fingers all routed to electrically conductive second traces disposed on a second layer of the package substrate that is a separate layer from the first layer of the package substrate, wherein none of the second traces are separated by non signal carrying traces,

the package substrate having electrically conductive traces on only the first layer and the second layer, and

electrically conductive contacts disposed on a second surface of the package substrate that substantially opposes the first surface,

the first traces all routed to a first set of the contacts that are all disposed within an innermost portion of the second surface, where the first set of contacts is disposed in at least one substantially concentric ring,

the second traces all routed to a second set of the contacts that are all disposed within an outermost portion of the second surface, where the second set of contacts is disposed in at least one substantially concentric ring at a peripheral edge of the second surface, and

a third set of contacts for power and ground only disposed interior to the first set of contacts on the second surface.

12. A packaged integrated circuit, comprising:

an integrated circuit having first bonding pads for high speed signals and second bonding pads for low speed signals,

a package substrate having,

electrically conductive bond fingers on a first surface of the package substrate, where the first surface is adapted to receive the integrated circuit in an attachment zone, the bond fingers disposed in at least two substantially concentric rings around the attachment zone,

the bond fingers of an innermost ring of bond fingers all routed to electrically conductive first traces disposed on a first layer of the package substrate,

the bond fingers other than those on the innermost ring of bond fingers all routed to electrically conductive second traces disposed on a second layer of the package substrate that is a separate layer from the first layer of the package substrate,

the package substrate having electrically conductive traces on only the first layer and the second layer, and

electrically conductive contacts disposed on a second surface of the package substrate that substantially opposes the first surface, the first traces all routed to a first set of the contacts that are all disposed within an innermost portion of the second surface, and the second traces all routed to a second set of the contacts that are all disposed within an outermost portion of the second surface,

first wire bonds having a first looping pattern electrically connecting the first bonding pads to the bond fingers of the innermost ring, and

second wire bonds having a second looping pattern that is different from the first looping pattern electrically connecting the second bonding pads to the bond fingers other than those on the innermost ring,

where the first looping pattern and the second looping pattern are separated by a spacing that reduces coupling between the low speed signals and the high speed signals, and a spacing between the first layer and the second layer reduces coupling between the low speed signals and the high speed signals.

Assignments (9)
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS LLC
To: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
Reel/Frame 073508/0807 →
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS CORPORATION
To: INVENSAS LLC
Reel/Frame 073508/0758 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
CHANGE OF NAME Recorded Jun 8, 2011
From: TESSERA INTELLECTUAL PROPERTIES, INC.
To: INVENSAS CORPORATION
Reel/Frame 026423/0286 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 29, 2009
From: LSI CORPORATION
To: TESSERA INTELLECTUAL PROPERTIES, INC.
Reel/Frame 023292/0897 →
CHANGE OF NAME Recorded Aug 11, 2009
From: LSI LOGIC CORPORATION
To: LSI CORPORATION
Reel/Frame 023075/0361 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 17, 2005
From: CHIA, CHOK J.; LIM, ALLEN SENG SOOI; OTHIENO, MAURICE O.
To: LSI LOGIC CORPORATION
Reel/Frame 016901/0844 →